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CLASS A1 
C-100-2010 




COURS 



UNIT V 

PREPARED EY 

NAVAL AIR TECHNICAL TRAINICG CEKTEf: 
NAVAL AIR STATION MEfAPHIS 
MILLINGTON, TENNESSEE 

PREPARED FOR 

NAVAL TECHNICAL TRAINING COMMAND 
CNTT*-M1635 R»v.i2/e4 


JANUARY 1983 




FOREWORD 


The purpose of this Student ' s Guide is to assist you through Digital 
Computer Theory and Troubleshooting, Unit 5, of the Advanced First- 
Term Avionics Course, The proper use of this guide will not only 
sharpen your theoretical troubleshooting skills, but will also aid 
you in the lab with actual hands-on practical work, troubleshooting 
the COM-TRAN Ten digital computer down to a defective component. 

The table of contents lists the page numbers for safety notices, 
Assignment Sheets, Information Sheets, Job Sheets, and Notetaking 
Sheets that will further enhance your abilities and skills as 
electronics technicians. 



SAFETY NOTICE 


As a Navy electronics technician, you will be required to perform 
safe and efficient maintenance on various types of electronic 
equipment. Not only your life, but the lives of many others will 
depend on your being safety conscious at all times. It is the 
responsibility of all Navy and Marine Corps personnel to prevent 
accidents. This can be done if everyone develops conscientious 
safety habits and observes all precautions when performing 
maintenance of any type. 



HOW TO USE THIS STUDENT'S GUIDE 

This Student's Guide has been prepared for you to use while you are 
attending the Advanced Term Avionics (Al) Course. Ample space has 
been provided for taking notes on the required lesson information. 
Remember, when you are in class, the information being provided by 
your instructor is information you will need in performing your Navy 
job. 

This volume contains the following: 

1. Assignment Sheets for most topics, to direct your study 
efforts . 

2. Information Sheets for some lessons, to provide additionl 
material for more difficult lesson topics. 

3 . Notetaking Sheets , containing lesson topic outlines will 
illustrations and ample space for personal notetaking. 

4. Job Sheet, to direct you in your first laboratory assignment. 


GOOD LUCKl Learn all you can 11 



UNIT V CLASS SCHEDULE 


Unit V is two weeks long, and starts in 

of the eighth week. The periods run 

period finishing half-way through the las y 


the fifth day 
with the last 
teneth week. 


The schedule is as follows: 


TOPIC NO. 

TYPE 

PERIOD 

TOPIC 

EIGHTH WEEK 

Fifth Day 

4.17 

Class 

313 

314 

315 

316 

Unit/Module Test: Criterion 
Test /written Examination 

5.1 

Class 

317 

318 

Introduction to Digital 
Computers 

5.2 

Class 

319 

320 

Mathematics of Digital 
Computers 

NINTH WEEK 

First Day 

5.2 

Class 

321 

322 

323 

324 

Mathematic s of Digi tal 
Computers 

5.3 

Class 

325 

326 

327 

328 

Basic Logic Gate 
Interpretation 

Second Day 

5.3 

Class 

329 

330 

Basic Logic Gate 
Interpretation 

5.4 

Class 

331 

332 

333 

Introduction to the COM -TRAN 
Ten 

Computer and Organization 

5.5 

Class 

334 

335 

336 

COM-TRAN Ten Logic and Data 
Plow 


iv 



TOPIC NO. 


TYPE 


PERIOD 


TOPIC 


Third Day 

Class 337 COM-TRAN Ten Software 

338 

339 

340 

341 

342 

343 

344 

Fourth Day 

5.7 Class 345 COM-TRAN Ten Hardware and 

Logic Diagram Data Flow 

346 

347 

348 

349 

350 

351 

352 


Fifth Day 

5 . 7 Class 353 


354 

355 

356 

357 

358 

359 

360 


COM-TRAN Ten Hardware and 
Logic Diagram Data Flow 


TENTH WEEK 
First Day 

5,7 Class 361 COM-TRAN Ten Hardware and 

Logic Diagram Data Flow 

362 

363 

364 

365 

366 

367 

368 


V 



TOPIC NO. 


TYPE 


PERIOD 


TOPIC 


Second Day 

5.8 Lab 369 

370 

371 

372 

5.9 Lab 373 

374 

375 

376 

Third Day 

5.9 Lab 377 

378 

379 

380 

381 

382 

383 

384 

Fourth Day 

5.9 Lab 385 

386 

387 

388 

Lab 389 

390 

391 

392 

Fifth Day 

Class 393 

394 

395 

396 

6‘i Class 397 

398 

399 

400 


COM-TRAN Ten Data Flow 
Analysis 


COM-TRAN Ten Fault I solation 


COM-TRAN Ten Fault Isolation 


COM-TRAN Ten Fault Isolation 


Unit/Module Test; Criterion 
Test/Performance Test 


Unit/Module Test: Criterion 
Test/Written Test 
Within-Course Comprehensive 
Test 1 

Written Examination and 
Review 

Introduction to Airborne 
Radar 


{Demo ) 


vi 



UNIT V HOMEWORK SCHEDULE 


All of the Assignment Sheets listed below shall be turned in when 
due. Each Assignment Sheet will be checked by an instructor for 
completeness and correctness. Failure to turn in an Assignment 
Sheet could result in disciplinary action. 


signment Sheet 

Period Due 

5.1 . lA 

321 

5 .2 . lA 

329 

5.3. lA 

337 

5.4.1 A 

337 

5.5.1A 

337 

5 .6. lA 

345 

5.7.1A 

369 


vii 



UNIT V LEARNING OBJECTIVES 


TERMINAL OBJECTIVE 

li.O ISOLATE an instructor-induced malfunction (under limited 
supervision) in an avionics, general purpose digital com- 
puter training device to a weapons replaceable assembly, a 
shop replaceable assembly, a stage, and a component and 
RECORD results on job sheets. Test equipment will be 
provided. Performance must be accomplished in accordance 
with COM-TRAN Ten Technical Operations Manual M104 , Vol. I. 
All general and personnel safety precautions must be 
observed, in accordance with OPNAVINST 5101.2 (series). 

ENABLING OBJECTIVES 


11.1 


11.2 


11.3 


11.4 


EXTRACT troubleshooting and performance data from given 
block and logic diagrams of a general purpose digital com- 
puter training device. All circuit performance and operat- 
ing characteristics will be documented on job sheets in 
accordance with specifications contained in COM-TRAN Ten 
Technical Operations Manual M104 , Vol. I. 

PERFORM visual inspections on an avionics general purpose 
digital computer training device for physical defects, 
security, integrity, and proper installation and RECORD 
results on a job worksheet. Performance must be accom- 
plished in accordance with procedures outlined in COM- 
TRAN Ten Technical Operations Manual M1Q4 , Vol. I. 

PERFORM operational and minimum performance cheeks (under 
limited supervision) on an avionics general purpose digitl 
computer training device and RECORD results on job data 
sheets. Necessary test equipment will be provided. 
Performance must be accomplished in accordance with COM- 

TRAN Ten Operations Manual M104 , Vol. I. All safety 

precautions must be observed in accordance with OPNAVINST 
5101.2 (series) . 

ISOLATE an instructor-induced malfunction (under limited 
supervision ) on an avionics general purpose digital computer 
training device to a weapons replaceable assembly, a shop 
replaceable assembly, a stage, and a component and RECORD 
results on job sheets. Test equipment will be provided. 
Performance must be accomplished in accordance with the 
COM-TRAN Ten Technical Operations Manual , Vol. I. All 
safety precautions must be observed in accordance with 
OPNAVINST 5101.2 (series). 


viii 



11.5 


document, on the VIDS/MAF, all necessary corrective actions 
required in a given maintenance situation to restore an 
avionic s general purpose digital computer training device to 
an operational condition . Documentation must include the 
ordering and receipt of parts. All documentation must be 
legible and in accordance with OPNAVINST 4790.2 (series). 


ix 



The other branch of the computer family stems from the graphic 
solution of the straighedge and compass problems achieved by ancient 
surveyors . Analogies were assumed between the boundaries of 
property and on the lines drawn on paper by the surveyor. Devices 
that relay on the analogous relationships that exist between the 
physical quantities associated with a problem under study are called 
analog computers . Analog solutions are obtained by measurement of 
some continually varying quantity, such as the fuel in a tank or the 
value of a modulated voltage. Such devices are referred to as 
continuous computers . 

Accuracy of computers 

The fundamental difference between analog and digital devices is 
that digital computers deal with discrete quantities while analog 
computers deal with continuous physical variables. The accuracy of 
an analog computer is restricted to the accuracy with which physical 
quantities can be sensed and displayed. This in turn is related to 
the quality of the components used in construction the computer; for 
example, the tolerance of electrical resistors or mechanical shafts, 
which would control the quality of the output representation. 

The concept of analog computation 



computat , L-iitii. xo , uiic: vai. xnvuxveu xn a car 
lation appear as continuous or smooth functions. As an example, 
consider the common clock as a computing device. Its function is to 
give an indication of elapsed time. It does this either by simpJ.e 
addition or by integration. A clock that keeps track of elapsed 
time by adding a discrete angular displacement to the hands each 
time a pendulum or balance wheel reverses direction or a timing 
pulse is received from a central control unit is a digital-computing 
device. (Almost all watches fall into this category.) The output 
of such a clock, an indication of elapsed time, changes in discrete 
steps. The size of the discrete steps varies according to the 
mechanism producing them. Some grandfather clocks advance the hands 
only once every minute; high-frequency pulse-controlled clocks 
change their output at such a rapid rate that to the observer the 
seems continuous. A clock that changes the position of the 
hand continuously with time, such as an electric cl^k, is an 

“ integrates, with respect to time, the 

uouslv chain^nn^,. ^ iTotor shaft and obtains a smooth, contin- 
angular velocity of the motor shaft and obtains a 

Thuron6‘'tvne"or®i^ Changing angular displacement of the hands, 
th^num^r Of o =^f^,=°"’P'^tes elapsed time digitally by counting 
the number of oscillations of a balance wheel or pendulum, the other 


2 



type computes in analog fashion by continuous integration. A little 
throught will convince the technician that the latter is a rather 
natural process. Very few phenomena in the physical world change in 
steps. The world is made up of quantities or variables 
continuously^^^^°^^ functions of time. These change smoothly and 

Development of digital computers 

science and Industry, there has been a growing need 
for high-^peed computing devices. Long, tedius calculations that 
take months to perform have impeded, to a considerable extents, the 
progress or scientific research and development. Time-consumina 

might take a human being years to do can be accom- 
?= vn in a matter of minutes with modern high-speed computers. It 
IS known that computers, when supplied with p^tinent dat^ can 

imnrnvL^f outcomes, guide missiles, determine production 
1 iprovements, play games of chess and checkers, write music, and 

fantastic speeds. How these things are accom- 
plished will be increasing interest to the avionios'^ratings. 

The purpose of this course is to remove much of the mystery 
surrounding digital computers by delving into their methods of 

science?" familiarizing the student with the language of the 


Functions of digital computers 

a?fn?rne? computers, like most recent discoveries, 

are not new. They have been used as long as man has been holdina 

DLr?h???ah°thrc^"f'''‘^"^"^^^r methods have changed! 

c?r?ulato?f ?nd fingers, adding machines, 

dif?eren? =°"’P“ters . The methods used by each are 

on logical caLuUtionl! 

thoughts that a computer can think-'-it cannot. Diqital 

knob Snlv knowledge as a d^r 

latino ^ f information is placed into them do any calcu- 

?= hnTii • . ^ ability to make that calculation. The ability 

sLlle ci?c"I?t? arrangements of relatively ^ 

simple circuits. When a computer performs an ooeratinn It tiool oo 

by comparing quantities representing data that Lve b?t; placed into 
It. Its output consists of coded numbers thaf mncf ^ 

matically decoded into some form of understandable language.^" 


3 



Data representation in digital computers 


The word "numbers" as applied to computers is misleading — coded 
numbers would be more descriptive of the machine language. Acutally 
numbers that represent information are merely a series of pulses and 
the absence of pulses, cleverly encoded to represent various 
letters, numbers items, operations, directions, or whatever else is 
desired . 


Anything can be represented by a code of a sort; for example, 
letters of the alphabet, numbers, towns, distances. Coded messages 
are nothing more than letters and numbers represented in other 
forms , or terms . In coded messages , the letter "A" may mean or igj.— 
nator, the number "6" may mean the letter "H, " etc. In digital com^- 
puters, some code bases on binary numbering is used. By employing 
binary 1 s and O's, represented by the presence and absence of 
electrical pulses, various things, such as letters and numbers, are 
represented. The reason for this method of coding will become 
apparent as you progress through this course. 


Description of digital computer units 

=°"tain blocks of circuits and machinery (see 
figure 1) that can be broadly broken down into: 


1 . Input unit . 

2 . Output unit . 

3. Memory unit. 


4. Arithmetic and logic unit (ALU). 

5. Control unit. 


throu'grwhich'inLr'm^tion'L'^^d^frth'P'""^- 

feeding information to the computer SpurunU^are used 

typewriter keyboard or magnetic tape. do ® 

thing— feed data to the computer sb that , io“ 

problem may be obtained. ^ logical solution to a 

The output unit translates the results 

;■ ;sks;°“ 


4 



The arithmetic and logic unit contains circuits that are relatively 
s imple . It accompli shed mathemat ic a 1 c ale ul at ions and performs 
logical operations. The arithmetic and logic unit is able to make 
logical decisions ^ by comparing quantities of data against each 
other. The solution to a given problem is sent from the arithmetic 
and logic unit to the memory unit, where it remains until needed for 
further calculations or until otherwise routed by the control unit. 


The control unti decodes instructions and generates timing and 
control signals, which cause the various units of the computer to 
function as an integrated system . 

Terms and definitions 

AUTOMATIC DATA PROCESSING (ADP) — processing performed by automatic 
means . 


ANALOG pertaining to representation by means of continuously 
variable physical quantities. 

ANALOG COMPUTER — (a) a computer in which analog representation of 
data is mainly used; (b) a computer that operates on analog data by 
performing physical processes on these data. 

ARITHMETIC UNIT— the unit of a computing system that contains the 
circuits that perform arithmetic operations. 

BIT — a binary digit. 

sequence of adjacent binary digits operated on as a unit 
usually shorter than a computer word. Most modern minicomputers 
have an 8-bit byte. 


CENTRAL PROCESSING UNIT--a unit Of a computer that includes the 
c ircuits controlling the interpretation and execution of 
instructions; synonymous with mainframe; abbreviated CPU, 


COMPUTp— a data processor that can perform substantial computation, 
inc luding numerous arithmetic or logic operations, without 
intervention by a human operator during the run. 


COMPUTER GENERATIONS— computers are sometimes classified by the 
follows^°'^ Hardware. Generally they are classified as 


a. First generation, vacuum tubes and relays. 

b. Second generation, semiconductors discrete devices 


5 




5 





c. Third generation, integrated circuits. 

d. Fourth generation, large-scale integration. 

CONTROL UNIT — a main functional unit of a CPU (central processor 
unit) responsible for instruction decoding and command and timing 
generation . 

DATA — (a) a representation of facts, concepts, or instructions in a 
formalized manner suitable for communication, interpretation, or 
processing by human or automatic means; (b) any representation, such 
as characters or analog quantities, to which meaning is or might be 
assigned . 

data processing — the execution of a systematic sequence of 
operations performed upon data : synonymous with information 
processing , 

data PROCESSOR“”a device capable of performing data processing, 
including desk calculators, punched card machines, and computers. 

DIGITAL — pertaining to data in the form of digits. 

DIGITAL COMPUTER — (a) a computer in which discrete representation of 
data is mainly used; (b) a computer that operates on discrete data 
by performing airthmetic and logic processes on these data. 

DISCRETE“-pertaining to distinct elements or to representation by 
means of distinct elements, such as characters. 

EXPLICIT ARITHMETIC — adding two numbers to form a total. 

FLOWCHART — a graphic representation for the definition, analysis, or 
solution of a problem, in which symbols are used to represent 
operations, data, flow, equipment, etc. 

GENERAL PURPOSE COMPUTER — a computer that is designated to handle a 
wide variety of problems. What it can do is mainly limited by its 
programs . 

HARDWARE physical equipment, as opposed to the computer program or 
method of use; e.g., mechanical, magnetic, electrical, or electronic 
devices. Contrast with software. 

HYBIRD COMPUTER — a computer for data processing, using both analog 
representation and discrete representation of data . 

IMPLICIT ARITHMETIC— comparing two numbers to determine which is the 
larger . 


6 



INFORMATION — the meaning that a human assigns to data by means of 
the known conventions used in their representation. 

INPUT DEVICES — the device or collective set of devices used for 
conveying data into another devic e . 

INTERFACE — a shared boundary. An interface might be a hardware 
component to link two devices or it might be a portion of storage or 
registers accessed by two or more computer programs. 

MEMORY — (a) pertaining to a device into which data can be entered, 
Field, and can be retrieved at a latter time? (b) loosely, any device 
that can store data; (c) synonymous with storage, one of the main 
functional units of a CPU (computer processor unit). 

NONVOLATILE MEMORY — a device that retains all the information it 
contains when power is removed. 

OFFLINE — pertaining to equipment or devices not under control of the 
central processing unit . 

ONLINE — (a) pertaining to equipment or devices under control of the 
central processing unit; (b) pertaining to a user's ability to 
interact with a computer - 

OUTPUT DEVICE“-the device or collective set of devices used for 
conveying data out of another device. 

PERIPHERAL EQUIPMENT — in a data processing system, any unit of 
equipment, distinct from the central processing unit, which may 
provide the system with outside communication. 

PROCESSOR — (a) in hardware, a data processor; (b) in software, a 
computer program that includes the compiling, assembling, 
translating, and related functions for a specific programming 
language . 

PROGRAM“-a series of instructions or statements, in a form 
acceptable to a computer, prepared in order to achieve a certain 
result. A person who is involved in the designing, writing, and 
testing of programs is called a programmer, and what he does is 
called programming , 

SOFTWARE — a set of computer programs, procedures, and possibly 
associated documentation concerned with the operation of a data 
processing system; e.g., compilers, library routines, manuals, and 
circuit diagrams. 

SPECIAL PURPOSE COMPUTER--a computer that is designed to handle a 
restricted class of problems. 


7 



TERMINAL — a point in a system or communication network at which data 
can either enter or leave. 

VOLATILE MEMORY — a device that loses all the information it contains 
when power is removed . 


8 



NOTETAKING SHEET 5.1. IN 


INTRODUCTION TO DIGITAL COMPUTERS 


REFERENCES: 


1. Burroughs Corporation. Digital Computer Principles . 
McGraw-Hill Book Company, 1969. Chapters 20, 21, 22, 

2. Digital Computer Basics . NAVTRA 10088-Bl , 1983. 

3. Malvino Albert P,, and Donald P. Leach. Digital Prin 

Applications . N.Y.; McGraw-Hill Book Company, 1975. 

14. 


NOTETAKING OUTLINE 

I . Terms and Definitions 


II. Classes of Computers 


N. Y. : 

and 2 3 . 


iples and 
Chapter 


9 




Block 









Types of Digital Computers 


Basic Computer Block 


11 



12 



fO 


INFORMATION SHEET 5.2.11 
MATHEMATICS OF DIGITAL COMPUTERS 


INTRODUCTION 

Digital computers operate in binary numbers , binary-coded numbers , 
nd binary-related-number systems, such as octal and hexadecimal, 
amiliarity with the structure and handling of these numbering 
systems is essential in understanding the arithmetic unit of a 
digital computer. The purpose of this information sheet is to 
provide you, the technician, with the basic concepts of computer 
numbering systems and the computer process of arithmetic. 


REFERENCES 


i- Digital Computer Basics . NAVTRADEC 10088-Bl, 1983. 

2. Malvino, Albert P., and Donald P. Leach. Digital Principle — ar^ 
Applications. N.Y.: McGraw-Hill Book Company. Chapter 2, 
pages 17-34; Chapter 13, pages 365-398. 

3. Williams, Gerald. Digital Technology . Chicago: Science 
Research Association, 1982. 


INFORMATION 

1. Terms and definitions 

a. Radix (base)— the number of characters used in a numner 
system. 

b. Radix point— the dividing point between whole numbers and 
fractions . 

G. Bit — a binary digit — either 0 or 1 . 

Byte — a sequence of binary digits acted upon as a 
unit— usually shorter than a computer word. 

e, word— a set of bit that occupies one storage location— 
usually consisting of two bytes. 

f. Modulas— the number of discrete conditions a device or 
system can indicate. 

1 n nnani-itv that completes the modulas or highest 

count'^rsys^L, frequently used to represent the negative 

of a quantity. 


13 




14 


h. Open“-end math — the process by which a carry or borrow 
generated by the most-sign if leant digit is disregarded. 

i. Closed-end-math — the process by which a carry or borrow 
generated by the most-significant digit is brought to the 
least-significant digit and added. 

j. Positional notation — a number system where the value of a 
digit depends upon its position, 

2 . Commonly used numbering systems include ; 

a . Decimal , radix 10 , 10 symbols / 0 through 9 

b. Binary, radix 2 , 2 symbols, 0 and 1 

c . Octal , radix 8, 8 symbols , 0 through 7 

c. Hexadecimal, radix 16, 16 symbols; 0 through 9 (first 10 
symbols) and A through F (last 6 symbols) 

3 . Positional notation 

a. The value of a digit depends upon the position of the digit 
within a number. The value of each position is equal to the 
radix raised to a power, 

b. The number "726]^0" equal to 7 x 10^ + 2 x 10^ + 6 x 10^. 


1 102 

loi 

10^ 

1 

! Power 

1 

1 100 

10 

1 

1 

1 Pos itional value 




1 in decimal 

i 7 

2 

6 

1 

1 Number (decimal) 

1 


FIGURE 2 - Decimal structure. 


15 



c. The binary number ''IOI2" is equal to 1 x 2^ + 0 x 2^- 4- 1 x 
2^, or 4 + 0 + 1 = 5^0 

Power 

Positional value 
in decimal 

Number (binary) 

FIGURE 3 - Binary structure, 

d. The octal number "526g" is equal to 5 x + 2 x 8^' h 
6 X sO, or 320 + 16 + 6 = 343^0 



Power 

Positional value 
in decimal 

Number 

FIGURE 4 - Octal structure. 



e. The hexadecimal number "lA9i6’' is equal to the following: 
1 X 162 + A(IO) X 16i + 9 X 16°, or 256 + 160 + 9 = 425io 



Power 

Positional value 
in decimal 

Number (hexadecimal ) 


Hexadecimal structure , 


16 


4. Conversion of numbering systems is easily accomplished. 


a, Changing decimal to binary, octal, and hexadecimal is done 
through division . Progressively, divide the decimal by the 
radix of the system to which it is being converted , record 
the remainder after each division, and continue division 
until the quotient becomes 0. 

b. Convert 26]^0 binary (radix 2). 

(1) Place in standard division form, 

2/'”^ 

(2) Divide 26 by the radix and record the remainder, 

13 

2/ 26 remainder of 10 

(3) Divide the quotient, "13," by the radix and record the 
remainder . 

6 

2 / 13 remainder of 1 

(4) Divide the quotient, "6," by the radix and record the 
remainder . 

3 

2 f ^ remainder of 0 

(5) Divide the quotient, "3," by the radix and record the 
remainder . 

1 

2/ remainder of 1 

(6) Divide the quotient, "1," by the radix and record the 
remainder . 

0 

2/ 1 remainder of 1 


(7) Conversion has been completed. 


17 



(8) Write the result. 


26]^0 ” 11010 2 

c. Convert 105]^0 octal (radix 8). 

(1) Place in standard division form. 

8/ 105 

(2) Divide 105 by the radix and record remainder. 

13 

8/ T05^ remainder of 1 

( 3) Divide the quotient, "13 , " by the radix and recoircd 
remainder . 

^ 

8/ 13 remainder of 5 

(4) Divide the quotient, "1," by the radix and recor<a 
remainder . 

O 

8/ i remainder of 1 

(5) Conversion has been completed. 

(6) Write the result. 

105io = 1518 

d. Convert 573i^0 hexadecimal (radix 16) 

(1) Place in standard division form. 

16 r~^ 

(2) Divide 573 by the radix and record the remaindeir . 

35_ 

16/ 573 remainder of 13 


the 


t-he 


18 



(3) Divide the quotient, “35," by the radix and record the 
remainder . 

^ 

16/ 35 remainder of 3 


(4) Divide the quotient, "2," by the radix and record the 
remainder . 

0 

16/ remainder of 2 


(5) Change remainders that are larger than 9 to hexadecimal 
value . 

13 = Die 

(6) Conversion has been completed. 

(7) Write the result. 

573io - 23 Di6 

5. Conversion of binary, octal, and hexadecimal to decimal is also 
easily done. The process is performed through multiplication 
and addition. Multiply the most significant digit (MSD) of the 
number by the radix. Then add the product to the next digit to 
the right and multiply again by the radix. Continue the process 
until the least-significant (LSD) has been added. 

a. Convert IIO 2 to decimal. 

(1) Write the binary number. 

1 1 O 2 

( 2 ) Multiply MSD by the radix ( 2 ) . 

1 

x2 

2 

(3) Add the product, “2," to the next digit to the right. 

1 

+2 

3 


19 



(4) Multiply the sum, "3," by the radix (2). 

3 

6 

( 5 ) Add the product, " 6 , " to the next digit to the right . 

0 

+6 


( 6 ) Conversion has been completed. 

(7) Write the result. 

IIO 2 = 6^0 

b. Convert I 5 I 3 to decimal, 

(1) Write the octal number. 

1 5 1 q 


(2) Multiply the MSD by the radix ( 8 ), 
15 1 

8 


(3) Add the product, " 8 ," to the next digit to the right. 
5 

X 8 

13 


(4) Multiply the sum, "13," by the radix ( 8 ). 
13 

X 8 

104 


(5) Add the product, "104," to the next digit to the right. 
1 

+ 104 
105 


20 



( 6 ) Con vers ion has been completed , 

(7) Write the result. 

1510 = iOS^o 

c . Convert 23D]^5 to decimal , 

(1) Write the hexadecimal number. 

2 3 Die 

(2) Multiply the MSD by the radix (16). 

2 

X 16 
32 

(3) Add the product, "32," to the next digit to the right. 

3 

+32 

35 

(4) Multiply the sum, "35," by the radix (16). 

35 

+ 16 
560 

(5) Add the product, "560," to the next digit to the right. 

13 (D) Refer to figure 1 for the value of (d), 

+ 560 
57 3 

(6) Conversion has been completed. 

(7) Write the result, 

23 Die ” ^ 10 


21 



6. Conversion of binary related systems 

a. Converting octal to binary is performed by grouping. Use 
groups of three binary digits and assign each digital a 
binary value. Then/ combine the groups. 

b. Convert 3I63 to binary (radix 2 ), 

( 1 ) Write the octal number. 

3 1 63 

(2) Start with the least-significant digit. 

( 3 ) Write the binary equivalent of each octal digit. 

3 16 

011 001 110 
{ 4 ) Combine the groups . 

011001110 


( 5 ) Conversion has been completed. 

(6) Write the result. 

3I63 = OIIOOIIIO2 


c . 


d. 


1 V C J, o 




SenaratA j,s perrormed by grouping, 

assign each three digits and then 

been%o::?"j^biL"th:°L\\rdigii:?"- 


Convert lOllOOOlOj to octal (radix 8). 
( 1 ) Write the binary number. 


IOIIOOOIO2 


(2) Start with the least-significant digit. 

( 3 ) separate the binary number into groups of three digit 
101 100 010 


22 



e 


(4) Write the octal equivalent of each group of binary 
digits . 

101 100 010 

5 4 2 

{ 5 ) Combine the octal digits 
542 

(6) Conversion has been completed. 

(7) Write the result. 

IOIIOOOIO 2 = 5428 

e. The conversion of hexadecimal to binary is performed by 
using four groups of binary digits. Assign each hexadecimal 
digit a binary value and then combine the groups. 

f. Convert 5 to binary (radix 2). 

(1) Write the hexadecimal number. 

5 Ai6 

(2) Start with the least-significant digit, 

(3) Write the binary equivalent of each hexadecimal digit, 

5 A(16) Refer to figure 1 for the 

hexadecimal value of (A) . 

0101 1010 

(4) Combine the groups. 

01011010 

(5) Conversion has been completed, 

(6) Write the result, 

5Ai6 = OIOIIOIO 2 


g. Converting binary to hexadecimal involves separating the 
binary numbers into groups of four digits. Assign each 
group a hexadecimal equivalent and then combine the groups. 


23 



h» Convert IIIIIOOI 2 to hexadecimal (radix 16). 

(1) Write the binary number. 

IIIIIOOI 2 

(2) Start with the least-significant digit. 

(3) Separate the binary number into groups of four digits, 
1111 1001 


(4) Write the hexadecimal equivalent of each group of binary 
digits. ^ 


1111 1001 
F 9 


Refer to figure 1 for 
hexadecimal equivlent , 


( 5 ) Combine the groups . 
F9 


( 6 ) Con vers ion has been completed • 

(7) Write the result, 

IIIIIOOI 2 ~ ^^16 

7, Binary arithmetic 


a . 


Addition is the direct method 
as in decimal , 


performed in the 


same manner 


b. Fundamental rules 


( 1 ) 0+0—0 with no carry 

(2) 0 + 1=1 with no carry 

(3) 1+0=1 with no carry 

(4) 1+1=0 with a carry of 1 

c. Add IOI 2 + IOI 2 

( 1 ) Place in column form. 

101 augend 
L addend 
sum 


24 



( 2 ) Add the first column . 
1 

+ 1 

0 with a carry of 1 


(3) Insert carry in next column and add, 

1 

0 

+ 0 

r with no carry 


(4) Add the last column. 

1 

+ 1 

0 with a carry of 1 

(5) The last carry is the most-significant digit of the 
sum. 

(6) Addition has been completed. 

( 7 ) Write the result of addition , 

IOIO 2 

d. Subtraction is the direct method performed in the same 
manner as in decimal, 

e . Fundamental rules 

(1) 0-0=0 with no borrow 

(2) 1-1=0 with no borrow 

(3) 1-0=1 with no borrow 

(4) 0 - 1 = 1 with a borrow 

f . Subtract IIO 2 “ 10l2» 

(1) Place in column form, 

110 minuend 
-101 subtrahend 
difference 


25 



(2) First column requires a borrow. 

NOTE: In binary, a borrow involves borrowing 2 from 

the next higher order column which also decreases 
that column by 1, 

(3) Borrow 2 from the next higher order column and place 
over first column . 

0 2 

- 1 1 0 


(4) Subtract first column. 

2 

1 

(5) Subtract next column. 

0 

0 

(6) Subtract last column. 

1 

zl 

0 


(7) Subtraction has been completed. 

(8) Write the result of subtraction. 

0 0 l2 


g* 


h. 


i . 


^ -w.i ujie ai 

manner as is in decimal. 




Fundamental rules: 

(1 ) 1 X 1 = 1 

(2) All other combinations are equal to 0 

Multiply 10I2 X II2, 


26 



(1) Place in column form. Develop on the chalkboard. 

101 multiplicand 
X 11 multipl ier 

partial products 
final product 

(2) Multiply the multiplicand by the least-significant digit 
of the multiplier. 

10 1 
X 11 

101 partial products 

(3) Multiply the multiplicand by the next digit of the 
multiplier . 

10 1 
X 11 

10 1 

101 partial products 


(4) Add the partial products. 

10 1 
10 1 

1111 final product 

(5) Multiplication has been completed, 

(6) Write the result of multiplication. 

1 1 1 1 2 

j. Division is performed by the direct method in the same 
manner as in decimal. 

k. Fundamentals rules 

(1) 1 f 1 = 1 

( 2 ) 0 1 == 0 

(3) The divisor can only go into the dividend one time. 


27 



1. Divide IOOIO 2 ^ 110 


(1) Place in standard division form. 

quotient 

110/ 10010 dividend 
divisor 


(2) Divide dividend by divisor. 
1 

110 / 10010 


(3) Subtract the divisor from the dividend, 
1 

110/“T0“010 

110 

110 


(4) Divide the difference by the divisor. 

U 

110/ 10010 
110 
110 
110 
0 

(5) Division has been completed, 

(6) Write the result of division. 

II2 

8. Complement arithmetic 


compleraent^arithmetic'?'^^Subtractio^'^^'^^°*^^°" apply to 
oUn and A + ( — B ) = DIPPPRpmpit tr., 1 « “p u 

in binary with the most-sigSf ieln^bit^ol 

being the sign bit. ^ ricant bit of the complement 


(1) A binary 1 indicates a negative value. 


28 



(2) A binary 0 indicates a positive value. 

(3) All math functions can be performed by adders, which 
requires fewer circuits. 

Types of complements 

(l) The l‘s complement is used in the addition of signed 
numbers ; subtraction is performed by addition . The 
rules for complementation are as follows; 

(a) Change each binary 1 to a 0. 

(b) Change each binary 0 to 1 . 


1 00010101 BINARY NUMBER I 

I I 

1 11101010 I's COMPLEMENT FORM I 

1 .^ -I 

FIGURE 6 - The I’s complement. 

(c) The I's complement of a number, using eight bits; 
OOOOIIOO 2 represents a +12 
IIIIOOII 2 represents a -12 

NOTE; The most-signif icnt bit is a 1 , indicating 
a negative number. 

(2) The 2's complement is used in the addition of signed 
numbers; subtraction is performed by addition. The 
rules for complementation are as follows; 

(a) Develop the I's complement of the binary number. 

(b) Add 1 to the I's complement. 


00010101 BINARY NUMBER 
11101010 I's COMPLEMENT 
+1 ADD 1 

lllOloTf 2's COMPLEMENT FORM 


FIGURE 7 - The 2's complement. 



(c) The 2's complement representation of a number, 
using eight bits 

OOOOIIOO2 represents a +12 

IIIIOIOO2 represents a --12 

NOTE: The most-significant bit is a 1 indicating 
a negative number. 

c. The I's complement method of addition is used with closed- 
end math and the rules are as follows : 

(1) Negative numbers are shown in the I's complement form. 

(2) Add the numbers, including the sign bit. 

(3) When a carry is generated by the sign-bit column, 
perform an end-around and add. 

(4) A negative answer will be in the I's complement form. 

(5) A positive answer will be in true binary form. 

d. Add (+13 ]^q) + (IIj^q) 

NOTE: Use 8-bit numbers for simplicity. 

(1) Both numbers are positive; no complementation is 
required • 

(2) Write the binary value of each number. 

+13 = 00001101 
+11 = 00001011 

( 3 ) Add the addend to the augend » 

00001101 

+00001011 

00011000 


(4) No carry was generated by the sign-bit column. 

(5) The result is a +24io in true binary form. 
00011000 


30 



e. Add (~13io^ 

(1) Write the I's complement of each number. 

-13 = 11110010 
-11 = 11110100 

(2) Add the complemented addend to the complemented 
augend . 

1 carry 
110010 
-fllllOlOO 
11100110 

(3) A carry was generated by the sign bit column. 

(4) Perform the end-around carry and add. 


11110010 

+11110100 

11100110 

+ 1 

11100111 


(5) The result is a -“2410 complement form. 

11100111 

f . Add (-13x0^ ^^lo) 

(1) Write ~13 in the I's complement form. 

-13 = 11110010 

(2) Write +11 in true binary form. 

+11 - 00001011 

(3) Add the addend to the complementd augend. 

11110010 

+00001011 

11111101 

( 4 ) No carry was generated by the sign-bit column . 

110010 

001011 

111101 


31 



(5) The result is a -210 complement fornu 

11111101 


g. Add (-IIjq) + (13j^q) 

(1) Write “11 in the I's complement form. 

“11 = 11110100 

(2) Write +13 in true binary form. 

+13 = 00001101 

(3) Add the addend to the complemented augend. 

1 carry 
11110100 
+ 00001101 
00000001 


(4) A carry was generated by the sign-bit column. 

(5) Perform the end-around carry and add. 

11110100 

+ 00001101 

00000001 

1 

00000010 


U lu f 

00000010 

closed-end math?"\hri?ules 

rules are as follows: 

(1) Complement the subtrahf>n^ ■ , 

and add. cend, including the sign bit, 

(2) Apply the rules fnr i • 

1 s complement . 

(3) Negative numbers are shown in th i . 

q - . the 1 s complement form, 

Sobtract (+i3io) - (+II 10 ). 

(1) Write the binary value 

^ ''Slue of each number. 

+13 = 00001101 
+ 11 == 00001011 


32 



( 2 ) Form the 1 ' s complement of the subtrahend . 

00001011 

11110100 

(3) Add the complemented subtrahend to the minuend. 


1 carry 
00001101 
+ 11110100 
00000001 

( 4 ) A carry was generated by the sign-bit column . 

(5) Perform the end-around carry and add. 

00001101 
+ 11110100 
00000001 
+ 1 
00000010 


(6) The result is a +2^0 true binary form. 
00000010 

j. Subtract (-IS^o^ 

(1) Write the I's complement of each number. 

-13 = 11110010 
-11 = 11110100 

{ 2 ) Form the 1 ' s complement of the subtrahend . 

11110100 

00001011 

(3) Add the complemented subtrahend to the minuend. 

11110010 

+ 00001011 

11111101 

(4) No carry was generated by the sign-bit column. 

(5) The result is a -2i^o I's complement form. 
11111101 


33 



k. Subtract (-ISio) 


(1) Write -13 in the I's complement form. 

-13 == 11110010 

(2) Write +11 in true binary form, 

+11 = 00001011 

(3) Form the I's complement of the subtrahend. 

00001011 

11110100 

(4) Add the complemented subtrahend to the minuend. 

1 carry 
11110010 
+ 11110100 
11100110 

(5) A carry was generated by the sign-bit column, 

(6) Perform the end-around carry and add 

11110010 

+ 11110100 

11100110 

+ 1 

11100111 

(7) The result is a -24^0 in 1 ' s complement form. 
11100111 

1. Subtract {+13io) - (-Hiq) 

(1) Write +13 in true binary form, 

+13 = 00001101 

(2) Write -11 in I's complement form. 

-11 = 11110100 

(3) Form the I's complement of the subtrahend. 

11110100 

00001011 


34 



( 4 ) Add the complemented subtrahend to the minuend . 

00001101 

+ 00001011 

00011000 

(5) No carry was generated by the sign-bit column. 

(6) The result is a +24]^0 true binary form. 

00011000 

u The 2's complement method of addition is used with open-end 
math . 

NOTE: The COM-TRAN Ten uses the 2's complement method of 

addition and subtraction. The rules are as follows: 

( 1 ) Add the numbers , including the sign bit , 

{ 2 ) A carry generated by the sign-bit column is disregarded . 

(3) A negative answer will be in the 2's complement form, 

( 4 ) A pos itive answer will be in true binary form . 

(5) Negative numbers are shown in the 2's complement form. 

1. Add ( + 13 ;j^q) + ( + 11]^q) . 

NOTE: Use 8-bit binary numbers for simplicity. 

(1) Both numbers are positive; no complementation is 
required . 

(2) Write the binary value for each number, 

+13 = 00001101 
+11 = 00001011 

(3) Add the addend to the augend, 

00001101 

00001011 

00011000 

( 4 ) No carry was generated by the sign-bit column . 

(5) The result is a +24]^0 true binary form. 

00011000 


35 



Add {>-13io) + (“llio) 

(1) Write the 2's complement of each number. 


o . 


->13 = 11110011 
-11 = 11110101 

(2) Add the complemented addend to the complemented augend, 

1 carry 
11110011 
+11110101 
11101000 

(3) Disregard the carry from the sign-bit column, 

(4) The result is a -24^0 in the 2's complement form, 
11101000 

p. Add (+13io) + (“11 iq) 

(1) Write +13 in true binary form, 

+13 = 00001101 

( 2 ) Write —1 1 m the 2 ' s component form , 

-11 = 11110101 

(3) Add the complemented addend to the augend. 

1 carry 
00001101 
11110101 
00000010 

(4) Disregard the carry from the sign-bit column. 

(5) The result is a +2io in true binary form. 

00000010 

q. Add (-13io) + 

(1) Write the -13 in thn i 

in the 2 s complement form, 

”13 = 11110011 



(2) Write the +11 in true binary form. 


+11 = 00001011 

( 3 ) Add the addend to the complemented augend , 

11110011 

+00001011 

11111110 

(4) No end carry was generated by the sign-bit column. 

( 5 ) The result is a -' 2 iq in the 2 ' s complement form . 
11111110 

r. The 2's complement method of subtraction is used with open- 
ended math. The rules are as follows; 

( 1 ) Complement the subtrahend , including the sign bit and 
add . 

( 2 ) Apply the rules for 2 ' s complement addition , 

(3) Negative numbers are shown in the 2's complement form. 

s. Subtract {+13 iq) - (tllj^oJ* 

(1) Write the binary value for each number. 

+ 13 == 00001101 
+11 = 00001011 

( 2 ) Determine the 2 ' complement of the subtrahend , 

00001011 

11110101 

( 3 ) Add the complemented subtrahend to the minuend . 

1 carry 
00001101 
+ 11110101 

(4) Disregard the carry from the sign-bit column. 

(5) The result is a +2^0 in true binary form. 

00000010 


37 



t. Subtract (-ISiq) “ • 

( 1 ) Write the 2 ' s complement of each number . 

“13 = 11110011 

“11 = 11110101 

(2) Form the 2's complement of the subtrahend. 

11110101 

00001011 

(3) Add the complemented subtrahend to the minuend. 

11110011 

00001011 

11111110 

(4) No carry was generated by the sign-bit column. 

result IS a - 2^0 in the 2's complement form, 
11111110 


u. Subtract (-ISiq) - (+II 10 ). 

(1) Write -13 in the 2's complement form 
"13 = 11110011 

(2) write fll in true binary form. 

+11 = 00001011 


(3) 


Form the 2 ' s complement of the 

00001011 

11110101 


subtrahend . 


(4) Add the complemented subtrahend to 

1 carry 
11110011 
11110101 
11101000 


the minuend. 


(5) Disregard the 

(6) The result is 

11101000 


carry from the 
^ “2410 in the 


sign-bit column. 

2 8 *^oniplement form. 


38 



V. Subtract {+13io) " (-llio). 

(1) Write +13 in true binary form. 

+13 = 00001101 

( 2 ) Write ~1 1 in the 2 ' s complement form . 

“11 11110101 

(3) Form the 2's complement of the subtrahend. 

11110101 

00001011 

(4) Add the complemented subtrahend to the minuend. 

00001101 

+ 00001011 

00011000 

(5) No carry was generated by the sign-bit column. 

(6) The result is a + 24 iq in true binary form. 

00011000 

9. Computer multiplication is calculated by three different 
methods , 

a. Multiplication by repetitive addition 

(1) Requires a counter to keep track of additions. 

( 2 ) Disadvantages is that it reqiaires too much time for 
large numbers. 

b. Multiplication by shifting left 

(1) In binary, this is the equivalent of multiplying by 2. 

(2) Disadvantage is that multiplication is limited to powers 
or ^ • 

c. Multiplication by addition and shift right 

( 1 ) Most common method used in digital computers . 

(2) Advantage is that it requires less time to perform. 

(3) The COM-TRAN Ten uses the addition and shift right 

method , ^ 


39 



10 , Multiplication, addition , and shift right 


a. The names and purposes of the registers used in the 

operation are as follows (refer to figure 8; note tliat this 
is a simplified algorithm flow chart of the COM-TRAN Ten)* 

(1) Accumultor register (A-register) 

{ a ) Holds the result of each addition . 


nuxQs rne two hign-order bytes of 
multiplication has been completed 


b. 


(2) Buffer register (B-register) holds the multiplicand 
during multiplication. 

(3) Quotient register (q register) 

(a) Holds the multiplier prior to multiplication. 

low-order bytes of the product after 
multiplication has been completed, 

(4) Countdown register (C-register) 

(a) Holds the number of shifts. 

(b) Number of shifts is the computer-word length, 

(c) COM-TRAN Ten word length is 8 bits. 

Multiplication operation of the COM-TRAN Ten 

reg\^s\frs: set up the 

Q-re.i.ter.. 

B-registL'"containr00001UK'’'®®'^®^®'' B-regiater: 

A-register: A-register contains 00000000. 
Sets c-reglster to a count of 8 : C-regiater containa 

C-register in the COM-TRAN Ten ia 8 bits. 


40 




B- REGfSTER 

— 

0 0 o 0 I I t I 


C- REGISTER A- REGISTER 


ooooim multiplicand 

X 000001 01 MULTIPLIER 
OlOOIOM PRODUCT 


O' REGISTER 



CLEAR 
A' REGISTER 


SET 

C-REGISTER 
TO -8 


On - 0 


ADO 
A TOB 


SHIFT 

A/ 0 - REGISTER 
RIGHT BY I 

DECREASE 
C-REGISTER 
BY -I 


C-REG.sO 


STOP 


Olio 


0 10 1 


0 10 0 


0 0 11 


0 0 1 0 


0 0 0 I 


0 0 0 0 


SHIFT 


Q 0 o 0 0 ^ I I I o o 0 o 0 I 

SUM A + B 

^ I I O 0 O 0 0 I 

SHIFT 

O 0 1001 01 100000 

SHIFT 

o[o|q[o[o|i |q[o I [o I 1 I I I O j 0 |o I O 
SHIFT 

0 I 0 I 0 I 0 I 0 I 0 I I [ 0 [ 0 I I I o I I I I I 0 I ^[o 

SHIFT 

OOOOOOOfl |o |o [ I j O [ I n io 0 i 

— — — — — — — — J — — — — I 

SHIFT 

-j — — — — 

00000000 lOOIOIIO 

■ * ' '* 1 * " i . ■ 1.. — I i t 

SHIFT ^ 

® ^ 0(001011 

ANSWER 

o 00000 ooj [oil |o I 0 I I I O I I I I 


e. ANALYSIS OF REGISTERS 


A, ALGORITHM FLOW CHART 


FIGURE 8 


multiplication by addition and SHIFT RIGHT 


41 























NOTE: Addition will no longer take place. The QO 
bit will remain 0; only the shifting of the 
AQ-register right will take place. 

(20) Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000100. 

(b) Q-register now contains 10110000. 

(21) Decreases C-register by 1: C-register now contains 

0100. 

(22) A decision is made. 

(a) C-register equals 0. 

(b ) Decision is no , 

(23) A decision is made. 

(a) QO bit equals 0, 

(b ) Decision is yes . 

(c) No addition takes place. 

(24) Shifts contents of AQ-reglster right one place. 

(a) A-register now contains 00000010. 

(b) Q-register now contains 01011000. 

(25) Decreases C-register by 1 : c-register now contains 

(26) A decision is made. 

(a) C-register equals 0. 

(b) Decision is no. 

(27) A decision is made, 

(a) QO bit equals 0. 

(b) Decision is yes. 

(o) No addition takes place. 


44 



Shifts contents of AQ-register right one place. 

Ca) A~register now contains 00000001. 

( b ) Q-register now contains 00101100 . 

Decreases C-register by 1: C-register now contains 
OOlO . 

A decisibn is made . 

( a ) C- register equals 0 , 

( b ) Decision is no . 

A decision is made. 

( a ) QO bit equals 0 . 

(b) Decision is yes. 

(c) No addition takes place. 

Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000000. 

Cb) Q-register now contains 10010110. 

Decreases C-register by 1: C-register now contains 

:>ooi . 

\ decision is made, 

[ sl ) C-register equals 0, 

[b) Decision is no. 

^ decision is made. 

! a) QO bit equals 0. 

b) Decision is yes, 

c) No addition takes place. 

Jhiifts contents of AQ-register right one place. 

a) A-register now contains 00000000. 

b) Q-register now contains 01001011. 


45 



NOTE; Addition will no longer take place. The ^ 
bit will remain 0? only the shifting of 
AQ-register right will take place, 

(20) Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000100. 

(b) Q-register now contains 10110000. 

(21) Decreases C-register by 1; C-register now contains 

0X00 t 

(22) A decision is made. 

(a) C-register equals 0. 

(b) Decision is no. 

(23) A decision is made. 

(a) QO bit equals 0. 

(b) Decision is yes. 

Cc) No addition takes place. 

(24) Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000010. 

(b) Q-register now contains OlOllOOO. 

(25) Decreases C-register by 1 : c-register now contains 


(26) A decision is made. 

(a) C-register equals 0 . 

(b) Decision is no. 

(27) A decision is made. 

{^) 00 bit equals 0. 

(b) Decision is yes. 

(c) No addition takes place. 


44 



(28) Shifts contents of AQ-register right one place, 

(a) A-register now contains 00000001. 

(b) Q-register now contains 00101100 . 

(29) Decreases C~register by 1: C-register now contains 
OOlO . 

(30) A decisibn is made, 

(a) C-register equals 0. 

( b ) Decision is no . 

(31) A decision is made. 

( a ) QO bit equals 0 . 

(b) Decision is yes. 

( c ) No addition takes place . 

( 32 ) Shifts contents of AQ-register right one place . 

(a) A-register now contains OOOOOOOO, 

(b) Q~register now contains 10010110, 

(33) Decreases C-register by 1: C-regiater now contains 
0001 . 

(34) A decision is made, 

(a) C-register equals 0. 

(b) Decision is no. 

( 35 ) A decision is made . 

(a) QO bit equals 0. 

(b) Decision is yes, 

(c) No addition takes place. 

(36) Shifts contents of AQ-register right one place, 

(a) A-register now contains OOOOOOOO. 

(b) Q-register now contains 01001011, 


45 



will no longer take place. The qO 
bit will remain 0; only the shifting of the 
AQ-register right will take place. ' 

t20) Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000100. 

(b) Q-register now contains 10110000 . 

(21) Decreases C-register bv !• r-r-crri 

0100. ^ y J- . G register now contains 

(22) A decision is made. 

(a) C-register equals 0. 

(b) Decision is no. 

(23) A decision is made, 

(a ) QO bit equals 0 , 

(b) Decision is yes . 

fc) No addition takes place. 

C24) Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000010, 

(b) Q-register now contains 01011000, 

(25) Decreases C-register bv 1- c-r^^rr-i 

0011, ^ y J- . G register now contains 


(26) A decision is made, 

(a) C-regiater equals 0, 

(b) Decision is no. 

(27) A decision is made, 

(a) QO bit equals 0, 

(b) Decision is yes. 

(c) No addition takes place. 


44 



(28) Shifts contents of AQ-register right one place. 

(a) A-register now contains 00000001. 

(h ) Q-register now contains 00101100. 

( 29 ) Decreases C-register by 1 ; C-register now contains 
0010 . 

(30) A decisibn is inade. 

( a ) C-register equals 0 . 

(b ) Decision is no . 

(31) A decision is made, 

( a ) QO bit equals 0 . 

(b) Decision is yes. 

(c ) No addition takes place . 

( 32 ) Shifts contents of AQ-register right one place . 

(a) A-register now contains 00000000, 

(b) Q-register now contains lOOlOllO, 

(33) Decreases C-register by 1; C-register now contains 
0001 . 

(34) A decision is made, 

(a) C-register equals 0. 

(b) Decision is no, 

(35) A decision is made. 

( a ) QO bit equals 0 , 

(b) Decision is yes . 

(c) No addition takes place, 

(36) Shifts contents of AQ-register right one place, 

(a) A-register now contains 00000000. 

(b) Q-register now contains 01001011, 


45 



C-register now contains 


(37) Decreases C-register by 1: 

0000 . 

(38) A decision is made. 


(a) C-register equals 0. 

(b) Decision is yes. 

(39) Stops, multiplication has been completed. 

(40) The product is displayed in the AQ-register : 
00000000 01001011 


11 


Computer division is done by three different methods, 
a. Division by repetitive subtraction 


Requires a counter to ]ceep track of subtractions. 

“ requirera for 


b. Division by shifting right 

(1) In binary, this is the equivalent of dividing by 2. 

(2) Disadvantage is that division is limited to powers of 






(1) Most common method used in digital oomputers . 

(2) Advantage is that it requires less time to perform. 

(3) ^e^COM-THAN Ten uses the shift-left-and-subtract 

12. Division, shift left and subtract 

The names and purposes of t-Via v 

tion are as follows (refer to “sed in the opera- 

simplified algorithm flL chLt ® 

w Chart of the COM-TRAN Ten), 

(1) Accumulator register (A-register) 

positive? subtraction when the result is 





C-REGISTER 




° 

3 


0 

• 

• 

3 


0 

■ 

• 

0 


0 

- 

0 

•] 



• 

0 



0 

B 

fl 

D 


IQ 

B 

B 

B 


B 

Q 

B 

fl' 


B 

B 

B 

B 


OQOtOOtO QUOTIENT 

oooooioo/oiooioi r dividend 

DIVISOR 


B-REGISTER 


0 

0 

0 

0 

0 

□ 

0 

0 

A- 

-REGISTER 





R 

0 

0 

0 

0 

0 

0 

0 

SHIFT 

0 

0 

0 

0 

0 

M 

0 

0 

SHIFT 

0 

0 

0 

0 

0 

0 

0 

□ 

SHIFT 

0 

0 

0 

0 

0 

0 

0 

0 

SHIFT 

B 

Q 

B 

□ 

Q 

D 

EH 

m 


Q-REGISTER 


'O 


0 

1 

0 

0 

j* 

0 

[T 

□ 


SHIFT 


1 I 

1 




— 1 

[ 

— 

uJ 

0 

0 

0 

0 

0 

LU 



SHIFT 


\V 

0 

' 

0 

±1 

1 

0 

0 

SHIFT 

\jo 

' 

0 

• 

1 

0 

0 

0 

SHIFT 

D 

Q 

n 

fl 

B 

B 

B 

D 


RESULT OF A-B 


□ 

B 

fl 

fl 

□ 

□ 

fl 

B 


B 

B 

n 


B 

B 

fli 

B 

SHIFT SHIFT 

□ 

B 

B 

□ 

□ 

B 

B 

n 


B 

II 

n 

B 

B 

B 

B 

B 

SHIFT 

SHIFT 

B 

B 

B 

□ 

B 

B 

n 

B 


D 

D 

□ 

□ 

B 

B 

Q 

B 

SHIFT 

SHIFT 

B 

B 

B 

Q 

Q 

B 

B 

D 

fl 

fl 

B 

□ 

B 

fl 

Qj 

B 

fl 

RESULT OF A-B 


B 

B 

Q 

□ 

B 

B 

B 

n 

B 

n 

B 

B 

B 

fl 

Q 

Q 

B 

SHIFT 

SHIFT 

□ 

□ 

D 

Q 

B 

B 

B 

fl 

■ 

fl 

□ 

Q 

B 

Q 

B 

B 

B 

answer 


B 

B 

B 

B 

B 

□ 

II 

B 

■ 

B 

□ 

B 

B 

B 

B 

B 

1 


8. ANALYSIS OF REGISTERS 


A. ALGORITHM FLOW CHART 


FIGURE 9 - Division by shift left and subtract. 


47 











(b) Holds the two high-order bytes of dividend prior to 
division . 

(c) Holds the remainder immediately after division 

(2) Buffer register (B-register) holds the divisor during 
division. 

(3) Quotient register (Q-register) 

(a) Holds the two low- order bytes of the dividend prioi' 
to division. 


(b) Holds the quotient immediately after division. 

(4) Countdown register (C-register) 

(a) Holds the number of shifts, 

(b) Number of shifts is the computer-word length. 

(c) COM-TRAN Ten word length is 8 bits. 

(5) Accumulator and quotient register (AQ-register ) 

dllring divide^^^^^^^^^ combined as one register 

AQ-reglster prior to 

Division operation 


registers. set up th 

(1) Dividend is loaded in the AQ-reglster. 

(a) AQ-register contains 00000000 01001011. 

( b ) A-regis ter contains OOOonnnn 

bytes of the dividend. bwo high-order 

(c) Q-register contains 01 om m i 

bytes of the dividend, two low-order 

B-gf:L^^:on1:^nrooXoT°^^ -register. 


48 



C-register contains 


(3) Set the C-register to a count of 8; 

1000 . 

NOTE: C-register in the COM-TRAN Ten is 8 bits. 

(4) A decision is made. 

(a) C-register equals 0. 

(b) Decision is no. 

(c ) When the C-register equals 0, division has been 
completed and the computer will stop. 

(5) Decreases C-register by 1: C-register now contains 

0111 . 

(6) Shift contents of A-register left one place. 

(a) The most-significant bit of the Q-register (Q7) is 
shifted into the least-significant bit of the 
A-register (AO) . 

(b) A-register now contains 00000000. 

( 7 ) Subtract the contents of the B-register from the 

A-register . 

NOTE: The 2's complement method of subtraction is used 

in the COM-TRAN Ten. 

(a) The result of subtraction is negative (11111100). 

(b) The most-significant bit of the result of subtrac- 
tion is called the F7 bit . 

(c ) The F7 bit is a 1 when the result of the subtraction 
is negative. 

(d) F7 (F7 not) is the complement of the F7 bit, F7 is a 
0 when the result of the subtraction is negative . 

(8) Shift contents of Q-register left one place. 

(a) The most-significant bit of the Q-register {Q7) is 
dropped . 

(b) F7 equals 0. 

(c) A "0" is shifted into the least-significant bit of 
the Q-register (QO). 


49 



(c2) Q-register now contains 10010110. 

(9) A decision is made, 

( a ) F7 bit equals 0 . 

(b) Decision is no. 

“ negative and is not 
transterred to the A-register. 

(10) A decision is made. 

(a) C-reister equals 0. 

(b) Decision is no. 

( 11 ) Decrease C"*ireciisi'p'r i • • 

9 y 1. C-register now contins 0110 . 

(12) Shift contents of A-register left one place. 

bit S the A-regLter!®''®*'®’' shifted into the AO 
(b) A-register now contains 00000001. 

L'rSsLr’:" B-register from the 

(a) The result of subtraction is negative (11111101). 

(b) F7 equals 1. 

(c) F7 equals 0. 

(14) Shift contents of Q-register left one place. 

{ a ) The mos t“Siqnif icant bi +- -p 4 -v. ^ ■ 

dropped. bit of the Q-register (Q7) is 

(b) F7 equals 0. 

the°Q-rlgistfr®(Qof° significant bit of 


(d) Q-register now contains 00101100. 


50 



(15) A decision is made. 

{ a ) F7 bit equals 0 . 

(b) Decision is no. 

(c) The result of subtraction is negative and is not 
transferred to the A-register, 

(16) A decision is made, 

(a) C- register equals 0 . 

(b) Decision is no. 

{ 17 ) Decrease C-register by one ; C-register now contains 
0101 . 

{ 18 ) Shift contents of A-register left one place , 

(a) The Q7 bi of the Q-register is shifted into the AO 
bit of the A-register . 

(b) A-register now contains 00000010, 

( 19 ) Subtract the contents of the B-register from the 
A-register . 

(a) The result of subtraction is negative (11111110). 

(b) F7 equals 1. 

(c) F7 equals 0. 

(20) Shift contents of Q-register left one place. 

( a ) The most-significant bit of the Q-register ( Q7 ) is 
dropped . 

(b) F7 equals 0 , 

(c) A ”0" is shifted into the least-significant bit of 
the Q-register ( QO ) . 

(d) Q-register now contains 01011000. 

(21) A decision is made. 

( a ) F7 bit equals 0 , 

(b) Decision is no . 


51 



( 22 ) 


(23) 


(c) The result of subt 
tiransf 0 irr 0 d to tli © 

A dec:ision is made. 

(a) C-register equals 

(b) Decision is no. 

Decrease C-register bv 

0100 , 


raction is negative and is not 
A-register . 


0 . 


1 s C-regis ter now contains 


(24) Shift contents of A-register left one place. 

Mt Of the L'regist^r!^^""’^ “ 

(b) A-register now contains 00000100, 

A-regL°Lr." B-register from the 

(a) The result of subtraction is positive (00000000), 

(b) F7 equals 0, 

(g) F7 equals 1. 

(26) Shift contents of Q-register left one place. 

Q-register (Q7) is 

(b ) F7 equals 1 . 

^ ^ shifted into the least-significant bit of 

the Q-register (QO), *=-i-yiij.ra.canT: oit ot 

(d) Q-register now contains 10110001, 

(27) A decision is made, 

(a) F7 bit equals 0, 

(b) Decision is yes. 

(O) The result of subtraction is positive. 


52 



(28) Transfer the result of subtraction to the A-register. 
A-register no contains 00000000. 

(29) A decision is made, 

(a) C-register equals 0. 

(b) Decision is no . 

(30) Decrease the C-register by 1: C-register now contains 
0011 . 

(31) Shift content of A-register left one place. 

( a ) The Q7 bit of the Q- register is shifted into the AO 
bit of the A~regis ter . 

(b) A~register now contains 00000001 . 

(32) Subtract the contents of the B-register from the 
A-register . 

(a) The result of subtraction is negative (11111101). 

(b ) F7 equals 1 , 

(c) F7 equals 0, 

(33) Shift contents of Q-register left one place. 

( a) The most-signif lent bit of the Q-register {Q7 ) is 
dropped . 

(b) F7 equals 0. 

(c) A "0" is shifted into the least-significant bit of 
the Q-register (QO). 

(d) Q-register now contains 01100010. 

(34) A decision is made. 

(a) F7 bit equals 0. 

(b) Decision is no. 

(c) The result of subtraction is negative and is not 
transferred to the A-register. 


53 



(35) A decision is made. 

(a) C-register equals 0. 

(b) Decision is no, 

(36) Decrease the C-register by 1: C-register now containc; 

0010. 

(37) Shift content of A-register left one place, 

(a) The Q7 bit of the Q-register is shifted into the AC 
bit of the A-register , 

(b) A-register now contains 00000010. 

(38) Subtract the contents of the B-register from the 
A-register, 

(a) The result of subtraction is negative (llllllio), 

( b ) F7 equals 1 . 

(c) F7 equals 0, 

(39) Shift contents of Q-register left one place. 

Q-register (Q7) is 

(b) F7 equals 0. 

the Q-register^(Q0?^° ^®^st-signif leant bit of 

(d) Q-register now contains 11000100. 

(40) A decision is made. 

(a) F7 bit equals 0, 

(b) Decision is no. 

(c) The result of subtraction 
transferred to the A-register?^^^^^'^^ 


54 



(41) A decision is made. 

(a) C-register equals 0. 

(b ) Decision is no . 

(42) Decrease the C~register by 1: C-register now contains 
0001 . 

(43) Shift content of A-register left one place. 

(a) The Q7 bit of the Q-register is shifted into the AO 
bit of the A-register . 

(b) A-register now contains 00000101. 

( 44 ) Subtract the contents of the B-register from the 
A-register , 

(a) The result of subtraction is positive ( 00000001 ) , 

( b ) F7 equals 1 , 

(c) F7 equals 0. 

(45) Shift contents of Q-register left one place. 

(a) The most-significant bit of the Q-register (Q7) is 
dropped , 

(b ) FT equals 1 . 

(c) A "1" is shifted into the least-significant bit of 
the Q-register (QO). 

(d) Q-register now contains 10001001 . 

(46) A decision is made. 

(a) F7 bit equals 0. 

(b) Decision is yes. 

( c ) The result of subtraction is positive . 

(47) Transfer the result of subtraction to the A-register. 
A-register now contains 00000001. 


55 



(48) A decision is made. 

(a) C-register equals 0. 

(b) Decision is no. 

(49) Decrease the C-register by 1: C-register now contains 

(50) Shift content of A-register left one place. 

(a) The Q7 bit of the Q-register is shifted into the aO 
bit of the A-register. 

(b) A-register now contains 00000011. 

(51) Subtract the contents of the B-register from the 
A-register . 

(a) The result of subtraction is negative (llllllll), 

(b) F7 equals 1, 

(c) F7 equals 0. 

(52) Shift contents of Q-register left one place. 

Q-register (Q7) is 

(b) F7 equals 1, 

^ shifted into the least-significant bit of 
the Q-register (QO ) . 

(d) Q-register now contains 00010010, 

(53) A decision is made, 

(a) F7 bit equals 0. 

(b) Decision is no, 

(o) The result of subtraction is negative and is not 
transferred to the A-regiater, 

(54) A decision is made. 

(a) C-register equals 0. 

(b) Decision is yes . 

(c) Stops, division has been completed. 


56 



BASE 10 

PURE BINARY 

GRAY CODE 

0 

0000 

0000 

1 

0001 

0001 

2 

0010 

0011 

3 

0011 

0010 

4 

0100 

0110 

5 

0101 

0111 

6 

0110 

0101 

7 

0111 

0100 

8 

1000 

1100 

9 

1001 

1101 

10 

1010 

1111 


FIGURE 10 - Comparison of digital, binary, and Gray code 



(55) The quotient is displayed in the Q-register; OOOlOOlO, 

(56) The remainder is displyed in the A-register: OOOOOOli. 
1 3 . Gray code 


a. Advantages include the reduction of operational errors. 
Gray-coded numbers change only one digit with each 
successive change in value. This property reduces the 
chance of errors. 


b. Gray code is commonly used 
the COM-TRAN Ten uses Gray 
pulses . 


in digital encoding circuits and 
code to initiate the clock 


. conversion 




' ■ vjiay euue ana zne conversion 

to Gray code (refer to figure 10). 

a. Binary to Gray code 

(1) Rules 

(a) The TOst-signif leant digit of the binary number will 
nLber digit of the Gray code 

the .^^st-significlnrd?gu!°"^'‘^^^' "i^h 

(c) The^sum of each addition is the next Gray code 

(d) Disregard any carries. 

''’rL°ch1S?" least-significant digit is 

( 2 ) Convert OIIO 2 . 

(a) Write the binary number. 

Olio 

(b) Write the (MSD) of fha k-! 

Of the Gray coL LmSer? <MSD) 

Q ^ 1 0 binary 

Gray code 


58 



(e) Continue until the least-signif lent digit is 
reached . 

(2) Convert 0101 to Gray code. Develop on the chalkboard. 

(a) Write the Gray code number. 

0 10 1 

(b) Write the (MSD) of the Gray code number as the (MSD) 
of the binary number . 

0101 Gray code 
0 binary 

( c ) Add the (MDS ) of the binary number to the next Grav 

code digit . ^ 

0 + 1=1 

(d) Write the sum as the next binary digit. 

0101 Gray code 

0 1 binary 

(e) Add the second binary digit to the third digit of 
the Gray code number. 

1 + 0=1 

(f) Write the sum as the next binary digit, 

0 10 1 Gray code 

Oil binary 

(g) Add the third binary digit to the last Gray code 
digit/ disregard the carry, 

1 + 1=0 

(h) Write the sum as the next binary digit. 

0101 Gray code 

0110 binary 

(i) Conversion has been completed, 

(j) Write the result. 

0110 binary 


60 



REFERENCES : 


NOTETAKING SHEET 5. 3, IN 
BASIC LOGIC GATE INTERPRETATION 


. William, Gerald. Digital Technology . Chicago: Science 

Research Association, 1982. Chapter 1, pp. 5-26, Chapter 2 , 
pp. 33-51; chapter 4, pp. 109-136; chapter 5, pp. 147-170. 

2. Fluke, John. Digital Logic Fundamentals . Merrill Publishing 
Company, 1977. Chapter 4, pp. 67-94; chapter 8, pp. 223-256; 
chapter 14, pp. 460-462. 


3 . 


Nat iona l Standard Graphic Symbols for Logic Diagrams . 
Electrical and Electronics Engineers, 1973, ANSI 
Y32.14, IEEE STD 91. MIL-STD-806C . Sections 1-6, 


NOTETAKING OUTLINE 
I. Definitions 


II. Logic Levels 

A. Positive logic 


POSITIVE LOGIC 
Logic 1 = +5 V = HIGH = H 
Logic 0 - 0 V = LOW == L 


FIGURE 1 - Logic level representation. 


61 



B . Negative logic 


NEGATIVE LOGIC 

Logic 1 = 5 V = HIGH = H 
Logic 0 = 0 V = LOW = L 

FIGURE 2 — Logic level representation. 


III. Negation Indicator System (logic) 


A. Description 


B. Application 


62 



IV. Logic Gates and Functions 


A. Amplifier 




3 

4 

3 — 

4 

L 

H 

L 

H 


3A. AMPLIFIER SYMBOL 3B. TRUTH TABLE 


FIGURE 3 - Amplifiers logic symbol and truth table . 
B. Inverter 



5 6 


L 

H 

H 

L 


4A Standard inverter symbol and truth table 


5 



1^ 

5 

6 



rn 


_ o 



IIJ 


4B Alternate inverter symbol and truth table 


FIGURE 4 - Inverter symbol and truth tables. 


63 



D » OR Gat© 




2 3 4 6 


L 

L 

L 

t 

L 

L 

H 

H 

L 

H 

L 

H 

H 

L 

1 

n 

Ji 

iL 

JL 

iL 


88 TRUTH TABU 


5a. 


FIGURE 8 - Standard OR symbol and truth 



figure 9 - or symbol and timing dia^r^r*- 


66 




E, NAND gate 


3 4 5 6 


L 

L 

L 

H 

L 

L 

H 

H 

L 

H 

L 

H 

H 

L 

L 

H 

H 

H 

H 

L 



FIGURE 10 “ Standard NTU^ID symbol and truth table. 



FIGURE 11 “ NAND symbol and timing diagram ■ 


67 





F. NOR gate 



2 

3 

4 

5 

L 

L 

l' 

H 

L 

L 

H 

L 

L 

H 

L 

L 

H 

L 

L 

L 

H 

H 

H 

L 


I2B TRUTH TABLE 


FIGURE 12 - Standard NOR symbol and truth table. 



figure 13 - NOR symbol and timing diagram. 


68 





F. 


Exclus ive OR 


\ Z 3 



FIGURE 14 - Standard EXCLUSIVE OR symlDol and truth table , 
G. Positive AND driver 



+ 6.3V I5B. TRUTH TABLE 

5A, POSTIVE AND DRIVER AND LAMP 

FIGURE 15 - Positive AND driver symbol and truth table. 


69 





H. Wired OR 



I6A. MIL. STD SYMBOL I6B. PHANTON OR SYMBOL 

FIGURE 16 - Wired OR symbols. 


+5V 



17 A. WIRED OR I70_ TRUTH TABLE 


FIGURE 17 - Wired OR configuration and truth table. 


70 




V. Logic Gate Equivalents 


A. De Morgan's theorem (law of duality) 


B . NAND gate and logic dual 


C . NOR gate and logic dual 


D. AND gate and logic dual 


VI, Flip-flops and Latches 
A. General information 


71 






73 


FIGURE 19 - NOR gate and AND equivalent. 




m 



CM 10 ♦ 


74 





75 


FIGURE 21 - R“S latch and truth table. 






UJ 

.J 

£0 

X 

H- 

a: 

H 


a: 

< 

tij 

o 

o 

2 : 

< 

h- 

UI 

</) 


m 





u 

2 

s 

u 

o 

Q 


H 

rCl 

(tJ 

4 J 

rC 

D 

-U 

c 

(d 

0 ^ 

0 

H 

4 ^ 

I 

(Xi 

•H 

H 

4-1 

<U 

<D 

Di 

tn 

•H 

-l-l 

I 

(U 


Q 


(U 


CA 

01 


9 

Oi 

p 

o 

H 


7 6 






B. R”S latch 


C. Type "D" edge-triggered flip-flop 


VII. Monostable Multivibrator (single-shot) 
A. General information 


B. Single-shot operation 


77 






lO 


t 

d) 

H 

fii 

4J 

rC 

4J 

3 

U 

4J 

G 


•(J 

0 


Q) 

iH 

c 

•H 



78 






NOTETAKING SHEET 5 . 4 . IN 


INTRODUCTION TO THE COM-TRAN Ten COMPUTER AND ORGANIZATION 


reference : 

Digiac Corporation . Technical Operations Manual for the COM-TR/'vN 
Ten M104 , Vol . I . Section III, pp. 13-36; section IV , pp. 37-127. 

NOTETAKING OUTLINE 

I. Operating Characteristics 


A. Memory Unit 


B . 


Arithmetic unit 



C. Control Unit 


D, Input section 


80 



E. Output section 


F. Teletypewriter 


81 



G. 


Logic circuit boards 


II. Control Panel 

A, Power and lamp test section 


82 



B. Input section 


C. l/O mode section 


83 



D . Control section 


E» Mode section 


84 



F. Error bypass section 


G. l/O section 


85 




86 


Ten control panel. 












o o 
» V 


>• 

oc 

QC 

< 

o 


a: 


ui 


uj V) o H 

^- Z < - 

^ UJ J 


= « lu 


< 

5 


u 

o 

W g > 

30 tJ — 

- < Q 


□□□□ □□□□ □□□ 

L§U LsJ Lo 


o o 
a o 


< 

h 

(/) 


cc 

q: 

hi 




o 




I 

CN 



87 



Ill . Display Panel 


A . Registers 


B. Condition code indicators 


88 



C . Status indicators 


D. Error detection indicators 


89 



IV. Instruction Repertoire 


Logic Timing 


90 



NOTETAKING SHEET 5 , 5 . IN 
COM-TRAN Ten LOGIC AND DATA FLOW 


REFERENCES 

Digiac Corporation. COM-TRAN Ten Technical Ope rations Manual M104, 
Vol. 1/ 1972. Section IV, pages 38“1 36 . ' ' 

NOTETAKING OUTLINE 


I . Key to Block Diagram 


II. Signal Busing 



Ill . Input Switches 


IV. I-register (input) 


92 



V. B-register {buffer ) 


VI . The 2 ’ s Compl erne n tor 


93 



VII, 


P-register (program address) 


VIII . 


S—register (op-code) 


94 



IX. Instruction Decoder (control "I" circuits) 


X. M-register (memory address) 


95 



XI , Memory Unit 


XII. X-register (index) 


96 



XIII . 


Index Adder 


XIV « Arithmetic Logic Unit (ALU) 


97 



• A-register (accumulator) 


XVI . 


Q-register (quotient) 


98 



XVII . C-register (countdown) 


XVIII. D-register (distributor) 


99 



XIX. Control Logic Circuits 


XX. Clock (500 kHz) 


100 



NOTETAKING SHEET 5.6. IN 


COM-TRAN Ten SOFTWARE 


REFERENCES: 

L. Digiac Corporation. Programming Manual for the COM-TRAN Ten 
M-107 , 1972. Section III, pp 24-36; section IV, pp 37-77. 

2. Digiac Corporation. TecTinical Operations Manual for the 
COM-TRAN Ten, M-104 , Volume I, 1972, Section III, pp 23-31; 
section IV, pp 64-127, 171-186. 

3. Digital Computer Basics . NAVEDTRA 10088B. 1978. Chapter 9 

pp . 210-228. 

NOTETAKING OUTLINE 

I, Programming Concepts 


A. Computer program 


B. Steps in programming 


1 . Statement 


2. Analysis 


3 . Flow chart 


4, Coding 



Debugging 


Documentation 



ir. Common Flowchart Symbols 


CZD 

TtHUINAL tVUBOL 


process SVNBOI. 



MANUAl IMPOT 5VWB(H. 


0ECIS10H STHBOL 


n o 


mput/outPuT SYMBOL 


PflEPARPTIOM SYMBOL 


PRtOEriNED PROCESS SYMBOL 


o 


CQWZCTCn SYMBOL 






AM«DYATIO«f tVifiOL 


FLCWLINC tYMIOLS 


FIGURE 1 “ Common flow chart symbols 

A. Terminal symbol 


B, Process symbol 


C. Manaual input symbol 


D, Decision symbol 


103 




E. Input/output symbol 


F . Preparation symbol 


Annotation symbol 


H. Predefined process symbol 


I. Connector symbol 


J . Flow line symbols 


104 



Ill, Program Coding Conventions 


A. Instruction code representation 


instruction 

name 

ADO il>flfi 

Arithmetic 
^ffO AccMituiiler 


mnemonic 

COOL 

AGO 

SFtA 

LOA 

>S1 


NUMINIC 

CQH 


aiNAAr 

CCOE 

Oi IQ OOO'J 

0001 OOC^ 

0010 OOCC 


lOOi lOOC- 


FIGURE 2 - Representation, mnemonic, numeric, and binary. 

1 . Mnemonic codes 

2 . Numeric code 

3 . Binary code 

B. Instruction word format 

1 . OP CODE 

2 . OPERAND 


105 



c 


Immediate instructions 


OP cooe 


□ □□□ □ Ddl® 


OPERAND 


[IlBCEia II][I]|^ 


FIGURE 3A - Immediate instruction format. 


D. Direct“indexed instructions 


□ □□□ □ 


-OP 


COOE 




uevQfly 

LEVELS 

□ SHI 

I I 


INOCV 
■ IT 


[I1II100 [I10Q0 

MEMORY ADDRESS 1 


ct-indexed instruction format. 


106 



E. Addressing upper memory 


nUUKt* ADDED 

rtlOh OADt'* 0i'5 yp OA-COOE 

UtUOXi AOLtOESS 


U1 *•» 

□ O 


FIRST level 


0 


iecokd level 


o 


TMKtO LlVtt 


3 rimdTii level 


meucr* lOC*' 


ooc 1L cvr 

If 6 

hod to -TF 

lE 

aoc^j TO 

100, ^ TO 


figure 4 “ Memory levels. 


Emit LivCL 


ICCOMD LEVEL 


rtMMTW level 




FIGURE 5 


Addressing memory levels 


for LDA instruction. 


107 



F» Index addressing 



FIGURE 6 - Index addressing for LDA instruction. 

IV. Instruction Repertoire 
A. General information 


B. Types of instructions 
1. Load instructions 


108 



store instructions 


3 . Arithmetic instructions 


4. Logical instructions 


5, Branch instructions 


6. Input/output instructions 


109 



V. 


Program Writing and Analysis 


A, Basic progranuting 

1 . Flov; chart 



FIGURE 7A “ Program flow chart. 


110 



Coding 



111 







Advanced programming 
1 , Flow chart 



FIGURE 8A - (A+B)^ - (C+D)^ 
Program flow chart and subroutine. 





2, Coding 



FIGURE SB - (A+B)2 - {C+D)2 Machine-coded. 


113 







114 



NOTETAKING SHEET 5 . 7 , IN 


COM -TRAN Ten HARDWARE AND LOGIC DIAGRAM DATA FLOW 


REFERENCES: 

TPchnical Operations Man ual for the COM-T RAN Ten, M-10_4, Volume I 
Digiac Corp oration, I'i'TT. Section IV, pp b9-136. 

NOTETAKING OUTLINE 

I. Key to logic Diagrams 


A. Inputs 


B. Outputs 


C, Logic symbols 


D. 


Phantom "OR" 


symbol 



II . Input Section 


A , Switch 1 circuits 


B. Switch 2 circuits 


116 



C* Switch logic 


D. l-register 


117 



Ill . Control Section 


A, 


B» D-register 


C. Decoder 


118 



Pulse 

Generolor 



119 


FIPURF. 



D. S-register 


E . Instruction decoder 


120 



F. P-register 


G. C-register 


121 



IV . Memory Section 


A. M-register 


B. Memory module 


C . X“Register/x“Adder 


122 



00 

SST.k 

Sense status 

8-bit status word ^ ACC 

01 

LCl,k 

Load COUNTDOWN immediate 
k - (C) 

02 

LAI,k 

Load ACCUMULATOR immedi, 
k -*■ (ACC) 

03 

|NX,k 

Increase INDEX 
(INDEX) + k ^(INDEX) 

08 

SKI.k 

Skip on INTERrupt 



k instructions 

09 

SKS.k 

Skip on SENSE 



k instructions 

OA 

SKF.k 

Skip on F LAG 



k instructions 

OB 

SLA,k 

Shift LEFT Arithmetic 
(AQ) to left k places 

10 

SRA,k 

Shift RIGHT Arithmetic 
(AQ) to right k places 

n 

OCD,k 

Output Command 
k + external device 

12 

LXl,k 

Load INDEX immediate 
k- (INDEX) 

13 

SLL,k 

Shift LEFT Logical 
(ACC) to left k places 

18 

5RL,k 

Shift RIGHT Logical 
(ACC) to right k places 

19 

AND,k 

AND 

k AND (ACC) - (ACC) 

lA 

IOR,k 

inclusive OR 
k OR (ACC) • (ACC) 

IB 

XOR.k 

Exclusive OR 
k EOR (ACC)-^ (ACC) 

20 

LDA.m.x 

Load ACCUMULATOR 
(m) - (ACC) 

28 

FLC,k 

FLAG clear 


0-> FLAG bit 

30 LCC.m.x Load Consecutive 

(m) -+ (m+1 ) 

38 LAN,m,x Load ACCUMU LATOR Negati 

(ACC) 

40 LD0,m,x Load QUOTIENT register 
(m)- (QUO) 

48 STA,m,x Store ACCUMULATOR 

(ACC)-^ (m) 

SO STX,m,x Store INDEX 

(INDEX)- (m) 

S8 STQ,m,x Store QUOTIENT 

(QUO) -v(m) 


60 ADD,m,x ADD 

(ACC) + (m)- (ACC) 

68 SUB.m.x SUBlract 

(ACC) - (m)-^ (ACC) 


70 

MPY.m.x 

Multiply 

(ACC) * (m) - (AQ) 

78 

DIV,m,x 

Divide 

(AQ) V (m) - (Q) 
remainder -+ (ACC) 

80 

RAO,m,x 

Replace Add One 
(m) + 1 - (tn) 

88 

RSO,m,x 

Replace Subtract One 
(m) - (m) 

90 

BUN.m.x 

Branch UNcondilional 
m- (PA) 

98 

BST,rn,x 

Branch & Stop 
fn PA STOP 

AO 

B5B,m,x 

Branch to Subroutine 

90 (BUN) - (m) 

(PA) - (m+1) 

(m+2)'^ (PA) 

A8 

BPS,rn,x 

Branch on Positive 
> 0 - m - (PA) 

BO 

BZE.m.x 

Branch on Zero 
= 0 - m - (PA) 

B8 

BNG,m,x 

Branch on Negative 
<0-m-(PA) 

CO 

BNC,m,x 

Branch on No Carry 

CARRY = 0 - m - (PA) 

C8 

BXZ.m.x 

Branch on INDEX Zero 
(INDEX) = 0- m- (PA) 

DO 

WDB,m,x 

Write Data Block 
(m) - external device 

D8 

MNO,m,x 

Manual Output 

(rn)-* (INPUT) & (BUFFER) 

EO 

RDB,m,x 

Read Data Block 

Data- (m) 

ES 

RDl.m.x 

Read until Interrupt 

Data (m) 

FO 

MNl,m,x 

Manual input 

(INDEX) & (BUFFER) - (m 

F8 

FLS,k 

FLAG Set 

1 ^ FLAG bit 


FIGURE 2 - Nurnerical listing of instructions. 


123 



V. Arithmetic Section 


A. B-register/2 ' s complemented/ selector 


B. A-register 


124 



C. ALU 


D. Q-register 


125 



VI. Output Section 


A. Lamp modules 1 and 2 


B. Inputs to lamp module 1 


C. Outputs from lamp module 1 


D. Inputs to lamp module 2 


E. Outputs from lamp nodule 2 


126 



VII. Logic Timing 



128 



JOB SHEET 5 . 8 . IJ 


COM-TRAN Ten DATA FLOW ANALYSIS 


INTRODUCTION : 

The purpose of this job sheet is to reinforce the classroom 
instruction on the COM-TRAN Ten and to familiarize you with its 
operation while the program is being monitored step by step through 
both the acquisition and execution phase of an instruction. 


LESSON TOPIC LEARNING OBJECTIVES: 


11.4.1. SELECT, from a given list, the statement describing the 
actions of the COM-TRAN Ten during the acquisition phase. 

11.4.2. SELECT, from a given list, the statement describing the 
actions of the COM-TRAN Ten during the execution phase, 

11.4.3. ANALYZE, a program using COM-TRAN Ten instructions, by 
listing the contents of the registers at any specified 
time during or after the execution of acquisition phase of 
the program, 


11.4.4. SELECT, from a given list with the aid of the HSI and the 
COM-TRAN Ten program, the statement correctly describing 
COM-TRAN Ten operations and data flow. 


REFERENCES: 


1. Digiac Corporation. Programming Manual f or the COM-TRAN Ten, 

M-107 , 1972, Section II, pp 29-36; section IV, pp 37-77. 

2. Digiac Corporation. Technical Operations Manual for the COM- 
TRAN Ten, M104 , Volume I, 1972. Section III ,'pp' 34-35 ; 
Section IV, pp 52-127, 


EQUIPMENT AND MATERIALS: 

COM-TRAN Ten Digital Computer Training Device (6F21). 


129 



JOB STEPS; 


Precautions to be observed 

1. Remove all exposed jewelry 

2. No food or drink allowed in the lab area. 

3. Instructor MUST be present when the equipment is 
energized . 

Step 1 . Initial equipment setup 

a. To obtain this condition, refer to paragraph 3~6 of 
the HSI. 


b. Complete the "Daily Inspection Check" as listed before 
continuing . 

Step 2 . Manual loading 


a. To load the program manually, refer to paragraph 
3“2--l of the HSI, table VII. 

b. Load the data listed in the table below in the 
computer . 


Program 

Address 


Mnemonic Code 

OP CODE 

OPERAND 

100 



LAI 

02 

07 

102 



LXI 

12 

01 

104 



MPY 

71 

oa 

106 



DIV 

7D 

07 

108 




03 


3 , Executing the 

Program 



a . 

Acquisition 

instruction 

Of the Load Accumulator Immediate (LAI) 


(l) Refer 

to 

paragraph 3-3 

of the HSI, 

table IX. 




130 



(3) Record the contents of the following registers; 

S-register 

M-register 

P-register 

D-register 

b. Execution of the (LAI ) instruction 

(1) Depress START switch. Ensure instruction was 
properly executed . 

(2) Record the contents of the following registers; 

A~register 

D~register 

c. Acquisition of the Load Index Register Immediate (LXI) 
instruction 

(1) Depress START switch. Ensure that the proper OP 
CODE and OPERAND are displayed on the panel. 

(2) Record the contents of the following registers; 
S-register 

M-register 

P-register 

D-register 

d. Execution of the LXI instruction 

(1) Depress START switch. Ensure that the instruction 
was properly executed. 

(2) Record the contents of the following registers; 

X- register 

D-register _____ 

e. Acquisition of the Multiply (MPY) instruction 

(1) Depress the START switch. Ensure that the proper OP 
CODE and OPERAND are displayed on the panel. 


131 



(2) Record the contents of the following registers; 

S-register 

M-register 

P-register 

D“register 


f . 


Instructor ' s Initials 


Execution of the MPY instruction by individual distributor 

pulses. Refer to paragraph 4-3-14 of the HSI for Logic 
Timing. ^ 


( 1 ) 


Select DIST mode. The computer is now ready to 
the multiply program. 


execute 


(2) DPO 

(a) Depress START. 

(b) Record the contents of the following registers! 
B-register 

C-register 

D-register 

C3) DPI (Note; IF B 7 = 0, computer skips DP2 and DP3 ) 

(a) Depress START. 

(b) Record the contents of the following registers: 
Q-register 

D-register 

(4) DP4 

( a ) Depress START. 

(b) Record the contents of the following registers: 
B-register 

D-register 


132 



(5) DPS 


( a ) Depress START, 

(b) Record the contents of the following registers: 

A-register 

D-register 

(6) DP6 

( a ) Depress START , 

(b ) Recor'd the contents of the fo llowing ; 

QO bit _____ 


D-register 

(7) DP7 

(a) Depress START. 

(b) Record the contents of the following registers 

A-register 

B~register 

D-register 

(8) DP8 

( a ) Depress START . 

(b) Record the contents of the following register: 

D-register 


(9) DP9 

(a) Depress START. 

(b) Record the contents of the following registers 

A-register 

Q-register 

D-register . 


133 



(10) DPIO 

(a) Depress START. 

Cb) Record the contents of the following registers 

C-register 

D~register 

(11) DPll 

(a) Depress START. 

(b) Record the contents of the following registers 

C-register 

D-register 

(12) DP6 

(a) Depress START. 

(b) Record the contents of the following: 

QO bit 

D-register 

(13) DP7 

(a) Depress START. 

(b) Record the contents of the following registers! 
A-register 

Q-register 

D-register 

(14) DPS 

(a) Depress START. 

(b) Record the contents of the following register: 
D-register 


134 



(15) DP9 


( a ) Depress START . 

(b) Record the contents of the following registers: 

A-register __________ 

Q-register 

D-register 

(16) DPIO 

( a ) Depress START » 

(b) Record the contents of the following registers; 

C-register 

D-register 


(17) DPll 

( a ) Depress START . 

(b) Record the contents of the following registers; 

C-register — — 

D-register 


(18) DP6 

( a ) Depress START » 

(b) Record the contents of the following; 

QO bit 


D-register 


(19) DP9 

(a) Depress START. 

(b) Record the contents of the following registers 

A-register — 

Q-register — 

D-register 


135 



(20) DPIO 


(a) Depress START. 

(b) Record the contents of the following registers 

C-register 

D-register 

(21) DPll 

(a) Depress START. 

(b) Record the contents of the following registers 

C-register 

D-register 

(22) DP6 

(a) Depress START. 

(b) Record the contents of the following: 

QO bit 

D~register 

(23) DP9 

(a) Depress START. 

(b) Record the contents of the following registers: 
A~register 

Q- register 

D-register 

(24) DPIO 

(a) Depress START. 

(b) Record the contents of the following registers: 
C-register 

D-register 


136 



(25) DPll 


(a) Depress START. 

(b) Record the contents of the following registers: 

C-register 

D~register 

(26) DP6 

( a ) Depress START . 

(b) Record the contents of the following; 

Qo 

D-register - 

(27) DP9 

( a ) Depress START . 

(b) Record the contents of the following registers; 

A-register — 

Q-register 

D~register 

(28) DPlO 

(a) Depress START. 

(b) Record the contents of the following registers 

C-register — 

(29) DPll 

( a ) Depress START . 

(b) Record the contents of the following registers 

C-register — — 

D~register — ■ “ 


137 



(40) DPIO 

( a ) Depre s s START , 

(a) Depress START. 

(b) Record the contents of the following registers: 

C-register 

D-register 

(41) DPll 

(a) Depress START 

(b) Record the contents of the following registers: 

C-register 

D-register 

(42) DP12 

DPI 3 (No operation) 

DP14 


(43) Continue depressing START until DP15 is displayed in 
the D-register (1F16). 

(44) DP15 

(a) Depress START, 

(b) Record the contents of the following: 

Condition code 

D-register 

A- and Q-registers 


Instructors initials 

g. Acquisition of the Divide (DIV) instruction by distributor 
pulses, (Refer to paragraph 4-2-1 of the HSI for logic 
timing. ) 

(l) Leave in the DIST Mode. The computer is now ready to 
acquire the DIV instruction. 

(2) Three facts regarding acquisition; 

(a) Always precedes execution. 


140 



(b) Is the same for all instructions . 

(c ) Is the phase where indexing takes place. 

( 3 ) DPAO 

(a) Depress START. 

(b) Record the contents of the following registers: 


M-register 

D-register .. 

(4) DPAl 

{ a ) Depress START . 

(b) Record the contents of the following registers: 

B-register 

D-register ^ 


(5) DPA2 

(a) Depress START . 

(b) Record the contents of the following registers: 

S-register 

D-register 


(6) DPA3 

{ a ) Depress START. 

(b) Record the contents of the following register: 
D-register 

(7) DPA4 

(a) Depress START. 

(b) Record the contents of the following registers: 

M-register 

D-register 


141 



(8) DPA5 


(a) Depress START. 

(b) Record the contents of the following registers: 
B-regi s ter 

D-register 

(9) DPA6 

(a) Depress START, 

(b) Record the contents of the following registers: 
M-r egister 

D-recjister 

(10) DPA7 


(a) Depress START. 

(b) Record the contents of the following registers: 

P"register 

D-register 

(11) DPA8 

( a ) Depress START. 

(b) Record the contents of the following registers: 
M-register 

D-register 

(12) DPA9 

(a) Depress START. 

(b) Record the contents of the following registers : 
M-register 

D-register 


142 



(13) DPAIO (NOTE: DPA II lihrough DPA 14 have no operation. ) 

(a) Depress START. 

(b) Record the contents of the following register: 
D-register 

(14) DPA15 

(a) Depress START. 

(b ) Record the contents of the fo 1 lowing register s 
D-register 

S-register 

M-register 

NOTE: Have instructor verify procedure*. Date: 

Instructor initicilsr 

h. Execution of the Divide (DIV) instruction by distributor 
pulses. (Refer to paragraph 4-3-15 of the HSI for logic 
timing. ) 

(1) Leave in t)ie DIST inode. The computer is now recidy to 
execute the DIV instruction. 

(2) Division is performed by the shift and add/subtract 
method . 

( 3 ) DPO 

(a) Depress START. 

(b ) Record the contents of the fo3J. owing registers : 

B-register 

C-register 

D-register 

(4) DPI 

(a) Depress START. 

(b) Record the contents of the following registe/s 

D-register 


143 



(5) DP2 (NOTE: If A 7 = 0/ computer skips to DP 6 . ) 

(a) Depress START. 

(b ) Record the contents of the following register ; 

D-register 

( 6 ) DP 6 

(a) Depress START. 

(b) Record the contents of the following register : 

D-register 


(7) DP7 

(a) Depress START, 

(b) Record the contents of the following registers 

C-register 

D-register 


( 8 ) DP 8 

(a) Depress START, 

(b) Record the contents of the following register; 

A-register 

D~register 


(9) DP9 

(a) Depress START. 

(b) Record the contents of the following registers 
Q-register 

D-register 


(10) DPIO 

(a) Depress START. 

(b) Record the contents of the following registers 

A~register 

D~register 


144 



(11) DP6 

(a) Depress START. 

(b) Record the contents of the following register: 

D-register 

(12) DP7 

(a) Depress START. 

(b) Record the contents of the following registers ; 

C~register 

D-register 


(13) DP8 

(a) Depress START, 

(b) Record the contents of the following registers: 

A-register 

D~register 


(14) DP9 

( a ) Depress START , 

(b) Record the contents of the following registers: 

Q-register 


D-register _____________ 

(15) DPIO 

(a) Depress START. 

(b) Record the contents of the following registers: 

A-register 


D-regi ster 


145 



(16) DP6 


(a) Depress START. 

(b) Record the contents of the following register: 

D”register 

(17) DP7 

( a ) Depress START . 

(b) Record the contents of the following registers 

C-register 

D-register 

(18) DPS 

(a) Depress START. 


(b) Record the contents of the following registers 

A-register 

D-register 

(19) DP9 


( a ) Depres s START . 

(b) Record the contents of the following registers 

Q- register 

D-register 

(20) DPIO 

(a) Depress START. 

(b) Record the contents of the following registers 
A-register 

D-register 


146 



(21) DP6 


(a) Depress START, 

(b) Record the contents of the following register: 

D-register 

(22) DP7 

(a) Depress START. 

(b) Record the contents of the following registers 

C-register . .. 

D-register 


(23) DP8 

(a) Depress START. 

(b) Record the contents of the following registers 

A-register . 

D-register 


(24) DP9 

(a) Depress START. 

(b) Record the contents of the following registers 

Q-register . 

D-register 

(25) DPIO 

(a) Depress START. 

(b) Record the contents of the following registers 

A-register 

D-register 


147 



(26) DP6 


( a ) Depress START . 

(ta) Record the contents of the following registers 
D-register 

(27) DP7 

(a) Depress START. 

(b) Record the contents of the following registers; 

C-register 

D-register 

(28) DP8 

(a) Depress START, 


Cb) Record the contents of the following registers; 

A-register 

D-register 

(29) DP9 

(a) Depress START, 

(b) Record the contents of the following registers; 

Q-register 

D-register 

(30) DPIO 

(a) Depress START. 

(b) Record the contents of the following registers; 

A-register 

D-register 


148 



(31) DP6 

(a) 

(b) 

(32) DP7 

(a) 

(b) 


(33) DP8 

(a) 

(b) 


(34) DP9 

(a) 

(b) 


(35) DPIO 

(a) 

(b) 


Depress START* 

Record the contents of the following register: 
D-register 


Depress START. 

Record the contents of the following registers 

C-register 

D-register 


Depress START. 

Record the contents of the following registers 

A-register 

D-register 


Depress START . 

Record the contents of the following registers 

Q-register 

D-register 


Depress START , 

Record the contents of the following registers 

A-register 

D-register 


149 



(36) DP6 


(a) Depress START. 

(b) Record the contents of the following register: 

D-register 

(37) DP7 

(a) Depress START, 

(b) Record the contents of the following registers; 

C-register 

D-register 

(38) DP8 

( a ) Depress START. 

(b) Record the contents of the following registers: 

A-register 

D-register 

(39) DP9 

(a) Depress START. 

(b) Record the contents of the following registers: 

Q-register 

D-register 

(40) DPIO 

(a) Depress START, 

(b) Record the contents of the following registers: 
A-register 

D-register 


150 



(41) DP6 


(a) Depress START. 

(b ) Record the contents of the following register : 

D-register _____ 

(42) DP7 

(a) Depress START. 

(b) Record the contents of the following registers ; 

C-register 

D-register 

(43) DP8 

(a) Depress START. 

(b) Record the contents of the following registers: 

A-register 

D-register 

(44) DP9 

(a) Depress START. 

(b) Record the contents of the following registers; 

Q~register 

D-register _____ 

(45) DPIO 

( a ) Depress START . 

(b) Record the contents of the following registers ; 

A-register 

D-register 


151 



(46) DP6 

(a) Depress START. 

(b) Record the contents of the following register: 

D-register 

(47) DPll 

(a) Depress START, 

(b) Record the contents of the following register: 

D-register 

(48) DP12 

(a) Depress START. 

(b) Record the contents of the following register: 

D-register 

(49) DP13 

( a ) Depress START . 

(b) Record the contents of the following register: 

D-register 

(50) DP14 

(a) Depress START. 

(b) Record the contents of the following registers 
D-register 


152 



(51) DP15 


(a) Depress START. 

(b) Record the contents of the following; 
Condition code 
D-register 

A~ and Q-registers , 

NOTE: Have instructor verify procedure. Date 

Instructor initials 


153 



SELF-TEST ITEMS 


1 . The purpose of the acquisition phase is to acquire the 

— the ' for execution. 

2. The bit used to determine Initiate Add (INA occurs during 
the MPY instruction and is the Q 0 /F 7 bit). (Choose one.) 


3. During DPI of the MPY instruction the data are tested for 

po ari ty . I f found negative# the 2 * s complementor would/would 
not be used. (choose one.) 


4. The "condition codes" are set at the end of the 
phase . 


the acquisition phase causes the contents of the 
X register to be added to the contents of the M-register? 


6 . During MPY# SC 8 is generated by 

7. DP15 of MPY occurs only when 


8 . 


Which bit controls whether the COM-TRAN Ten 
during the DIV operation? 


adds or subtracts 


9 . With^ the exception of the shifting required to attain proper 

^ step on the Job Sheet of the MPY instruction 

was the correct answer formed? 


10 . "Indexing" is accomplished by adding the contents of the 

the ^ contents of the .-register during 

acquisition?^ cJisplayed in the D-register during the 
True. False. 


is"pSsT?i?li 


154 



13, The COM-TRAN Ten used both addition and subtraction to 
execute this DIV funciton? True, False. 


14. Which distributor pulses make up the Divide Group (DVG)7 


15 . The "remainder" is the 2 ' s complement when the 
negative . 


is 


16. A DIV error signal may be generated at DP , DP t or 

DP 

17 . List both the MPY and DIV problems in decimal form. 


18. During the DIV process i When will a 1 be shifted into the 
Q-register? 

When “ 


155 



156 



NOTETAKING SHEET 5,8. IN 


COM-TRAN Ten DATA FLOW ANALYSIS 


REFERENCES: 

1. Digiac Corporation. Programming Manual for the COM~TRAN Ten , 
M--107 , 1972. Section II, pp 29-36; section IV, pp 37-77. 

2. Digiac Corporation. Technical Operations Manual for the 
COM-TRAN Ten, M-104 , Volume I, 1972. Section III, pp 34-35; 
section IV, pp 52-127, 

NOTETAKING OUTLINE 

I, Safety 


A. Discussion 


B. Lab Safety 


1 . Personal safety items 


2 . 


Equipment safety items 



II. Job Sheet 5.8. IJ 


A. Three stages 


1. Initial equipment setup 


2 . Manual loading 


3. Executing the program 


158 



B . Three processes 


1. Acquisition phase 


2. Execution of multiply 


3, Execution of divide 


C . Additional requirements 


III* Stand-by and Secure Procedures 


A. The stand-by condition 


B. The secure condition 


C. Usage 


159 



160 



NOTETAKING SHEET 5. 9. IN 


COM-TRAN Ten FAULT ISOLATION 


REFERENCES: 


1. Digiac Corporation. COM-TRA N Ten Technical Operations 

M104 / Vol. 1 , 1972. 

2. Digiac Corportion. Programminq Manual for the roM-TRaK? 

M104 . 1972. — — ■ 

LESSON TOPIC LEARNING OBJECTIVES 

11 . 2.1 


11 .3.40 

11 .3.41 

11 .4.5 


PERFORM a daily inspection on a digital computer trainer 
using a given HSI as reference, ^ 

PERFORM a preoperational checlc on a digital computer 
trainer, using a given HSI as reference. 

PERFORM an operational check on a digital computer 
trainer, using a given HSI as reference. 

ISOLATE, with the use of given test equipment, logic 
diagrams, and an HSI, an instructor-induced malfunction, 
following all procedures outlined in the HSI for the 
digital computer trainer 6F21 and observing all safety 
precutions ♦ 

DOCUMENT, on the data sheet provided, using given test 
equipment and an HSI: abnormal indications, failing 
subroutine, failing instruction, failing phase of 
instruction, failing distributor phase, failing 
subcommand, and problem location, 

DOCUMENT, on the VIDS/MAF provided, all necessary 
corrective actions to simulate restoration of an 
ins tructor— induced malfunction on a digital computer 
trainer. 

NOTETAKING OUTLINE 

I. Safety 

A. Personal safety items 


11 .4.6 


11 .5.1 


161 



B. Equipment safety 


II. Test Equipment Setup 

A. VIDS/MAF and data sheet entries 


B. Logic probe lamp indications 


162 



C. Troubleshooting Procedures 


1. Step 1: Daily inspection 


. Step 2 : Preoperational check 


Step 3: Operational check 


4, Step 4; Subroutine check 


163 



5. Step 5: Acquisition/execution check 


6» Step 6: Isolation to problem 


7. Step 7: Signal-tracing 


164 



III. vids/maf 


IV. standby and Secure Procedures 
A. Standby procedure 

B « Secure procedures 


165
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